JPS60120464A - Interrupt control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention (d) @Ming's Technical Field The present invention relates to an interrupt control method between two microprocessors.

fb) Prior art and problems: Interrupt processing between two microprocessors (hereinafter referred to as processors). Here, suppose an interrupt request is issued from a processor to processor B. Conventionally, the interrupt processing in processor B is A temporary storage method has been adopted in which a circuit is set by an interrupt request and is reset upon completion of processing. In a processor that uses one task for control and processing, if processor A issues interrupt requests in succession, subsequent interrupt requests will be ignored while processors B and S are executing the processing task. (Since there is only one task, it cannot operate as a control task for accepting interrupts).

(c+ Purpose of the Invention The present invention has been made to solve the above-mentioned drawbacks,
The object of the present invention is to provide an interrupt control method that facilitates processing of interrupt requests.

+d) Configuration of the invention The present invention includes a first processing device and a second processing device,
In a processing system in which a second processing device accepts interrupt processing by issuing data specifying an interrupt level and an interrupt request from a first processing device, means for temporarily storing the interrupt request X; The second processing device includes means for clearing the temporary memory, an interrupt prohibition flag, and means for determining the flag, and when the first processing device issues the interrupt request, the second processing device receiving the interrupt request and setting the interrupt thread flag based on information in the temporary storage means;
The interrupt tlilJ(ill As described above, the present invention uses two microprocessors (M
When performing interrupt processing between two MPUs,
A register for temporarily storing interrupt requests and an interrupt thread flag circuit are provided. from the first MPU to the second MPU
What if an interrupt request is issued to? When it is L, the second MPU accepts the interrupt request and sets the interrupt prohibition flag according to the contents of the register in which the interrupt request is set. After the reception process is completed, the second MPU resets the contents of the register, and -1 the first MPU is designed to issue the next interrupt request when the interrupt thread flag is cleared. It is something.

te+ Examples of the Invention The present invention will be explained below with reference to the drawings. The drawing is a block diagram illustrating an embodiment of the present invention.

The embodiment is an example in which a microprocessing unit (hereinafter referred to as MPU) 1 in the drawings requests interrupt processing to MPU 2. Note that when the MPUI issues an interrupt request to the MPU 2, when the address (machine number) data A is output from the address bus 3, the signal level of the output terminal a of the decoder 4 becomes "0".This sets the register 5. ,
Since the signal level of the output terminal Q becomes "0", Iv
An interrupt is notified to the iPU2 (its interrupt input terminal I 1tQt ). Subsequent interrupts from that tiger are prohibited. Note that the interrupt level notification data D (8 bits) set in the buffer 7 prior to this is transferred to the buffer 10 via tristate gates 8 and 9. Next M
After receiving the interrupt request from the MPU 1 and completing the related processing, the PU 2 outputs the reception data E from the address bus 11. As a result, the signal level of the output terminal C of the decoder 12 becomes "o", and the register 5 is reset. Therefore, the signal level at the output terminal Q of the register 5 changes from "o" to "l". This rise change is detected by the rise detection section 13, and a pulse P is output at this time.

Along with this, register (for interrupt notification) 14 is set,
The signal level at the output terminal Q becomes rOJ, and is notified to M)) Ul via the interrupt input terminal Σ.

When the MPUI receives an interrupt notification from the MPU 2, it confirms with the decoder 4 (output terminal b) that the signal level of the interrupt prohibition flag F of the tri-state gate 6 is "L", and then issues the next interrupt. Submit a request.

(f) Effects of the Invention As described above, the present invention has a control means for sequentially processing interrupts that occur between two microprocessors that operate asynchronously, and therefore has the advantage of smooth and reliable interrupt processing.

[Brief explanation of the drawing]

The drawing is a block diagram illustrating an embodiment of the present invention,
The symbols used in the figure are as follows. 1.2 is Microprocessing Uni (MPU). 3.11 is address bus, 4.12 is decoder, 5゜1
4 is a register, 6, 8.9 is a tri-state gate, 7
．． 10 is a buffer, 13 is a rising edge detection section, 15 is a data bus, A is address (machine number) data, a. b, c, d are decoder terminals, D is data for interrupt level notification, F is interrupt No entry/exit flag, IRQ.

Claims (1)

[Claims] ml processing device and a second processing device, and when the first processing device issues an interrupt request X, the second processing device k accepts the interrupt processing,
means for temporarily storing the interrupt requirement X; means for clearing the contents temporarily stored in the storage means; and an interrupt prohibition flag;
when the first processing device issues the interrupt request, the second processing device accepts the interrupt request based on the information in the temporary storage means; After setting the interrupt thread flag and completing the reception process for the interrupt request, the second processing device is notified of the end of the reception process by clearing the contents of the temporary storage means. An interrupt control method that uses percentage values.