JPS6042496B2 - Parity error processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system for processing information using a processor and memory of a computer or a microcomputer, and particularly to a parity error processing method that occurs during memory access.

Conventionally, when processing parity errors in the memory of this type of information processing equipment, when a parity error occurs, processing is performed depending on the device that accessed the memory or the state in which the memory was accessed. There was no difference in the type of report when reporting the occurrence of a parity error.

In other words, if a parity error occurs in memory,
Processing in the processor was always the same. Therefore, this method has the disadvantage that when a parity error occurs, it is not possible to cause the processor to perform different processing depending on the difference in the importance of the data in which the parity error has occurred. . The purpose of the present invention is to eliminate these drawbacks, and for this purpose, when a memory parity error occurs, the type of device that started (accessed) the memory and the state of the memory at the time it was started are detected. By reporting different forms to the processor depending on the difference, the processor can execute different processing depending on the difference in the importance of the data in which the parity error has occurred.

- Hereinafter, the present invention will be explained in detail with reference to the drawings.

The figure shows one embodiment of the present invention, and a portion A surrounded by a broken line in the figure shows a control device having a processor.

Here, 1 is a processor, 2 is a main memory, and 3 is a parity addition and check circuit that adds a parity signal when writing to the memory 2, performs parity verification when reading from the memory 2, and monitors the stored data in the memory 2 for errors. , 4 is a status display register that displays the presence or absence of external input, processing status, etc., 5 is an interface unit that exchanges information with external device B, and 6 is a DMA (Direct MemO
ryAccess) transfer control circuit; 7 is a parity error processing circuit that sends a fault report with different contents to the register 4 depending on the situation at the time of occurrence when a parity error occurs; 8 is a bus in the control device A; shows. The parity error processing circuit 7 can be composed of, for example, an inhibit gate 11 and an AND gate 12 connected to the information lines P and q, and sends the output of each gate 11 and 12 to the register 4. When the external device B exchanges information with the main memory 2, it is also possible to do so without going through the processor 1 each time.

That is, when the interface unit 5 is activated through the external device B, the interface unit 5 activates the DMA transfer control circuit 6. Drl! The 4A transfer control circuit 6 controls the direct information transfer between the external device B and the main memory 2.
This is possible by using the control clock of the processor 1. While information is being transferred between external device B and main memory 2, a signal representing the state is supplied to parity error processing circuit 7 through information line p. The parity error addition and check circuit 3 adds a parity bit when storing information to the main memory 2, and performs a parity check when taking out information from the main memory 2. If a parity error is detected during the parity check, the parity error addition and check circuit 3 sends a parity error detection signal to the parity error processing circuit 7 through the information line q. send out the issue. In this parity error processing circuit 7, when the occurrence of a parity error is notified through the information line q, the parity error is processed so that the main memory 2 directly transfers information with the external device B by DMA control. It is possible to identify whether the parity error occurred during the process or during control with the processor 1 by the status signal received through the information line p. In this way, when a memory parity error occurs, the parity error processing circuit 7 converts the parity error into one that occurred during memory access from the processor 1 and the operation of the DMA transfer control circuit 6. It is possible to report to the status display register 4 separately from those that have occurred during the period. Thus, the processor 1 performs necessary processing by looking in the contents of the status display register 4. Note that for highly real-time processing, it is also possible to interrupt the processor 1 from the status display register 4. If a memory parity error occurs, the status l display register 4 determines whether the parity error occurred during memory access from the processor 1 or if the TIL was generated during the operation of the DMA transfer control circuit 6.
Since the display is performed by distinguishing whether the
It is possible to perform different processing depending on the accessed device. In the above example, when a parity error occurs in the main memory 2, the parity error processing circuit 7 identifies whether it occurs during access from the processor 1 or during DMA transfer control. However, even when the DMA transfer is not in progress,
The present invention can be applied.

That is, when there are multiple devices accessing the main memory 2, a status signal indicating which device is accessing the main memory 2 is sent to the parity error processing circuit 7 through the information line.
By supplying the signal to the parity error processing circuit 7, the parity error processing circuit 7 can grasp the device that has accessed the main memory 2, and can send different reports to the status display register 4 depending on the type of the device. In addition, the processing status of various devices is displayed through the information line p, and the parity error processing circuit 7 sends different reports to the status display register 4 depending on what kind of processing the device is performing. By doing so, the processor 1 can perform different processing depending on the processing state of the control device. As explained above, according to the present invention, the parity error processing circuit 7 changes the content of the report to the processor 1 according to the type or state of the device that accessed the main memory 2, thereby improving the memory parity error processing circuit 7. When an error occurs, the processor 1 can grasp the state and type of data being processed in the main memory 2, which has the advantage of being able to perform different processes depending on the importance of the data.

For example, for facsimile image signals that are allowed to have some code errors, no special measures are taken unless parity errors occur frequently, and the frequency of error occurrence is simply monitored.For program data, abnormalities are immediately handled. By doing so, it is possible to eliminate the need for excessive processing on signal parts where errors are allowed, and to create an economical program structure that does not require unnecessary processing. .

[Brief explanation of drawings]

The drawing is a block diagram showing an embodiment of the configuration of the present invention. A: Control device, B: External device, 1
...Processor, 2...Main memory,
3... Parity addition and check circuit, 4.
...Status display register, 5...Interface unit with external device, 6...DMA transfer control circuit, 7...Parity error processing circuit, 8...・
...Device bus, 11... Prohibition gate, 12.
...and gate.

Claims (1)

[Claims] 1 In a parity error processing method that includes an error check/error check code generation circuit that adds a parity signal when writing to the memory and performs parity verification when reading from the memory when performing information processing using a processor and memory. , by introducing an information signal representing the usage state of the memory and a parity error detection signal sent from the error check/error check code generation circuit, to generate a plurality of types of error detection signals corresponding to the types of the information signal. 1. A parity error processing method, comprising: an error processing means for sending out a parity error, and configured to appropriately change the content of a parity error report to the processor.