JPS60116219A - Transversal form automatic equalizer - Google Patents

Abstract

PURPOSE:To attain automatic equalization even under the control in an optional delay time by forecasting an error rate of an output signal of an automatic equalizer by a monitor and controlling the weight coefficient of each tap of a delay circuit so as to minimize the error rate. CONSTITUTION:Signal of channels I, Q of a 4-phase PSK signal are fed respectively to delay circuits 1-1-1-4, 2-1-2-4. The outputs of the delay circuits are fed respectively to adders 3-1 and 3-2 via weight coefficient circuits C-21- C21, C-2Q-C2Q, C'-2Q-C'2Q, C'-2I-C'2I', and each output of the adders is fed to discrimination circuits 4-1, 4-2. Each identification circuit compares the output with a reference value VR and outputs respectively outputs D0, D'0 eliminated with waveform distortion. Since the outputs of adders 3-1, 3-2 have similar waveform distortion, the output of the circuit 3-2 is inputted to an error monitor 5. When the outputs of discrimination circuits 51, 52 comparing a reference value VR with a smaller reference value V'R are different, the monitor 5 gives an output of an error pulse to a control circuit 6. The circuit 6 counts the error pulse, changes sequentially the coefficient values of the weight coefficient circuits and minimizes the error pulse generating rate.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a transparsal equalizer for removing waveform distortion used in digital multiplex radio systems.

(2) Technology background When the frequency band of the transmission path is limited.

In order to remove transmission path distortion, a transversal equalizer consisting of multiple tapped delay circuits is used. The delay time between taps is 1 time slot) To (T(1
= l/clock frequency), the zero hosing method, mean square method, etc. are known, but if the delay time is one time slot), then for example T. /2 etc., the existence of the control method is guaranteed mathematically, but the actual hardware is not clear.

(3) Purpose of the Invention An object of the present invention is to predict the error rate in the demodulated signal output from a transversal automatic equalizer using an error rate monitor, and to estimate the error rate determined by the error rate monitor. Based on the idea that the weighting coefficient of each tap of the delay circuit is controlled such that the delay time is minimized, and the control is performed by a microcomputer, for example, the delay time of the delay circuit is set to one time slot T.

(4) The purpose of the invention is to enable automatic control even at any time other than the above, thereby making it possible to reduce power consumption and shorten delay circuits (delay lines). According to the invention to achieve the above-mentioned objects.

a plurality of series-connected delay circuits receiving input signals;
A weighting coefficient circuit connected to the input/output of each delay circuit, an adder for adding the outputs of each shaping coefficient circuit, and comparing the output of the adder with an optimal value that minimizes waveform distortion. and a first discrimination circuit for transmitting an output signal using a transversal type automatic equalizer, the weighting coefficient value of the weighting coefficient circuit being made variable to remove waveform distortion of the output signal. a second discriminator circuit identical to the first discriminator circuit; a third discriminator circuit for comparing the output of the adder with a value smaller than the optimum value; A false alarm monitor composed of multiple exclusive OR circuits connected to the output of the third identification circuit is provided, and the weighting coefficient value of the weighting coefficient circuit is controlled so that the false alarm occurrence rate of the false alarm monitor is minimized. A transversal automatic equalizer is provided.

(5) Examples of the invention The present invention will be explained below with reference to two drawings.

FIG. 1 is a book circuit diagram showing an embodiment of a transversal automatic equalizer according to the present invention.

FIG. 1 shows a baseband transversal automatic equalizer for a four-phase PSK signal.

The input signal of channel E is supplied to four series-connected delay circuits 1-1 to 1-4, and the input signal of channel Q is supplied to four delay circuits 1-1 to 1-4 connected in series.
The signal is supplied to delay circuits 2-1 to 2-4 connected in series. Delay circuits 1-1 to 1-4 are weighting coefficient circuits cc-...
, C2*C-2Q C-10*-2I, 11°..., C2, and the adder 3-1. 3-2, and the delay circuits 2 to 1 to 2-4 are weighting coefficient circuits c f c-/ . . . , c';

-2Q# IQI 2Q . . . are respectively connected to adders 3-1 and 3-2 via C2. Each adder 3-1. The output of 3-2 is sent to the identification circuit 4-1. 4-2 respectively. This identification circuit 4-1. 4-2 is composed of multiple binary discriminators,
That is, it is compared with the reference value vR.

Identification circuit 4-1. 4-2 sends out outputs from which waveform distortion has been removed, and D0', respectively. On the contrary, the identification circuit 4-
1. 4-2 input signal, i.e. adder 3-1゜3-
The output signal of No. 2 may contain waveform distortion. Here, adder 3-1. 3-. The two outputs are mutually orthogonal components) and have equivalent waveform distortion.

Therefore, 1 weighting coefficient is set as Cac=C.

Adder output 3-1. 3-2 Both waveform distortions can be equalized0 Therefore, in order to monitor the waveform distortion in the output signal of the above-mentioned adder 3-2, an error monitor 5 is provided. In this error monitor 5, the identification circuits 51.52 and 4-1. It has the same configuration as 4-2, but the identification circuit 51
In this case, the optimal threshold voltage that minimizes the rate of error occurrence due to waveform distortion is given as the reference value VR, while in the discrimination circuit 52, a voltage that is smaller or larger than the above-mentioned optimal threshold voltage is given as the reference value VR. It is given as a reference value vR'.

Therefore, the identification circuit 52 generates more errors due to waveform distortion than the identification circuit 51.

The output of the exclusive OR circuit 53 includes two discrimination circuits 51 .
False signals appear only when the outputs of 52 are different.

The control circuit 6 counts the above-mentioned erroneous signals of the error monitor 5 and outputs the weighting coefficient circuits c'c'-..., C2Q-2I,
l engineering.

The control circuit 6 is configured, for example, as a microcomputer, by sequentially changing the weighting coefficient values of the control circuit 6, thereby minimizing the rate of occurrence of erroneous pulses.

FIG. 2 is a detailed block circuit diagram of the control circuit 6 of FIG. 1. In Figure 2, 61 is a CPU (central processing unit)
, 62 is a digital input port for inputting the erroneous signals of the erroneous signal monitor 5.

63 is a counter for counting the erroneous pulses.

64 is a RAM (
Random access memory), 65 is a moyr for storing programs such as processing routines, fixed data, etc.
read-only memory). Cash register, '-ta 66-1~
66-10 is a weighting coefficient circuit c', 2-piece.

This is for storing the weighting coefficient values of C-1I', . . . , C2Q. Supplied. Tsuma J), D/A converters 67-1 to 67-1
0 is the weighting coefficient circuit C-2I', C-z', "'m C
2Q (D weight coefficient value in registers 66-1 to 66-10
There is a means to set the value based on the stored value.

The operation of the circuit shown in FIG. 2 will be explained with reference to the flowchart shown in FIG. This operation starts at step 301 and sets i to 1 at step 302.

This value i is the weighting coefficient circuit C-a,'s c-1I's.
..., c′,.

In this case, it represents the number of ``c-2''.

C-1I's ++, ``'QQ 01 * '4 m
"', c, . In other words, in step 302, the weighting coefficient circuit C-21' (
=C1) was specified again. The weighting factors for orthogonal channels are given by Ci = C'i. however,
In the following steps, the i-th weighting coefficient circuit C1
Let me explain.

In step 303, the CPU 61 operates the counter 63 to count the number of error pulses from the error monitor 5 for a predetermined period of time, and stores the counted value as N1 in the first area of the RAM 64 together with the value of the register 66-i.

Next, in step 304, the specified weighting coefficient circuit Ci
After increasing the weighting factor value of by a certain amount.

An operation similar to step 303 is performed. That is, C
PU61 reads value Ci of register 66-i, and C6←
Perform the calculation Ci+ΔC (constant amount).

Ci is stored in register 66-i again. Therefore.

The weighting factor value increases by a fixed amount. After that, CPU6
1 operates the counter 63 to count the number of erroneous pulses from the erroneous pulse monitor 5 for a predetermined period of time, and stores the counted value as Nl in the second area of the RAM 64 together with the value of the register 66-i.

Next, in step 305, the specified weighting coefficient circuit C
After decreasing the weighting factor value of i by a certain amount.

An operation similar to step 303 is performed. That is, C
PU61 reads value C1 of register 66-i.

Ci4+ 06-2 Δc (certain amount) Null operation is performed and C6 is stored in register 66-i again. Therefore, the 2 weighting coefficient value decreases by a certain amount. CP[J61 operates the counter 63 to count the number of erroneous sibuluses from the erroneous simulator monitor 5 for a predetermined period of time, and stores the counted value as N3 in the register 6.
6-i is stored in the third area of the RAM 64.

That is, at this stage, the first and second
．． The third area contains the original value of register 66-i.
given that.

First area: Ci, N.

Second area: Ci+ΔC,N.

Third area: Ci-ΔC,N.

This means that data will be stored.

In step 306, the smallest one of Nl and N□Nm is determined. That is, the CPU 61 uses the RAM 64
The data N, , N, , N are sequentially read out and compared, and the area in which the minimum value is stored is determined.

Next, in step 307, the optimum value of register 66-i is read out from the area of RAM 64 where the minimum value determined in step 306 exists, and the optimum value of register 66-i is read out.
Set to .

In step 308, i≧M(register 66-io
number, in this case, 10).

If i<%, in step 309, i + − i + 1
Then, the processes of steps 303 to 308 are performed again.

If i≧M, the process advances to step 302, and the processes of steps 303 to 308 are performed again with i←1.

That is, register 66-1. 66-2. ....

The values 66-10 are rewritten to the optimal values in this order.

As a result, the number of occurrences of false alarms due to waveform distortion in the false alarm monitor 5 is reduced.

In addition, in the above-mentioned embodiment, the register 66-- has 3
Although the minimum value of the error occurrence rate for each location is determined by setting one value, it goes without saying that the number of set values may be different.

FIG. 4 is a block circuit diagram showing another embodiment of the transversal automatic equalizer according to the present invention.

In FIG. 4, a passband type (IP type) transversal type automatic equalizer is shown. In FIG. 4, C8 to C8 are weighting coefficient circuits, 11-1, 11-2 are delay circuits, 12-1. 12-2 is an adder, which is similar to the element in FIG.

Adder 12-1. The output signal of 12-2 is integrated by the 90° hybrid circuit 13 and supplied to the demodulation circuit 14. The demodulation circuit 14 outputs the waveform distortion removed,
Send D,'. An error monitor 15 is connected to the demodulation circuit 14, and a control circuit 16 is further connected to the error monitor 15.

Error monitor 15. The configuration of the control circuit 16 is also similar to that of the error monitors 5 and 6 shown in FIG.

(6) Detailed Description of the Invention According to the present invention, the delay time T of the delay circuit is one time slot). Control can be performed automatically even when the
It is expected that the delay line) will be shortened.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a transversal automatic equalizer according to the present invention, and FIG. 2 is a detailed block circuit diagram of the control circuit 6 shown in FIG. 1. FIG. 3 is a flowchart for explaining the circuit operation of FIG. 2, and FIG. 4 is a block circuit diagram showing another embodiment of the transversal automatic equalizer according to the present invention. 1-1 to 1-4. 2-1 to 2-41 11-1.11-2 ” Delay circuit 3-1.3-2.13-1.13-2: Adder 4-1
．． 4-2: Identification circuit 5.15: False 9 monitor 6.16: Control circuit Figure 2 Tiger

Claims (1)

[Claims] 1. A plurality of series-connected delay circuits that receive input signals, a weighting coefficient circuit connected to the input and output of each of the delay circuits, and adding the outputs of each of the shaping coefficient circuits. A useless adder and
a first identification circuit that compares the output of the adder with an optimal value that minimizes waveform distortion and sends out an output signal; In a transversal automatic equalizer designed to remove distortion, a second discrimination circuit is the same as the first discrimination circuit, and a third discrimination circuit that compares the output of the adder with a value smaller than the optimum value. and an erroneous signal monitor consisting of a plurality of exclusive OR circuits connected to the outputs of the second and third identification circuits, and the weighting coefficient is set such that the erroneous signal occurrence rate of the erroneous sensor monitor is minimized. A transversal automatic equalizer characterized by controlling weighting coefficient values of a circuit. 2. A first storage means for storing weighting coefficient values of each of the mold coefficient circuits, a counting means for counting the number of errors of the error monitor, and a second memory for storing the number of errors of the error monitor. and means for setting weighting coefficients for each of the shaping coefficient circuits based on the weighting coefficient values stored in the first storage means. sequentially setting a plurality of values for one weighting coefficient value stored in the first storage means, and sequentially storing the number of occurrences of errors in the error monitor for each of the units in the second storage means; determining the minimum number of occurrences of the stored number of erroneous occurrences;
Claim 1, wherein the weighting coefficient value of the weighting coefficient circuit is controlled by re-storing a set value corresponding to the minimum number of occurrences of v4 as the weighting coefficient value in the first storage means. Transversal type automatic equalizer described. 3. The transversal automatic equalizer according to claim 1, wherein the second identification circuit is shared with the first identification circuit.