JPS58206254A - Generating and inspecting system of error detecting code - Google Patents

Abstract

PURPOSE:To realize a generating/inspecting system of error code which has an inspecting function for each channel with a reduced number of component parts, by performing a calculation of CRC every time the block of a frame is received and then detecting an error when the end block is received. CONSTITUTION:The header part of a block is held at a register 122 from an input data 101, and the data 101 is held at a register 105 after obtaining an exclusive OR with a data 103. This OR value is stored in the 1st bit of a cell and then stored in the 2nd bit of a cell (i) which is held in the register 105 after obataining an exclusive OR with the value of the bus 3. These actions are repeated hereafter, and the result of CRC calculation is held at the cell (i). Then if the received header part is equal to a channel (j), a register 108 is equal to (j). Thereafter the block which is operated in the same way is at the end of an (i) channel frame, the value of (i) is loaded to a register 112. While an input data is fed to a shift register 114, and the output 117 of a comparator 116 is stored in an FF 119. Then the result of error detection is delivered.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a detection code generation tJy/inspection method used in data transmission to improve transmission quality.

Conventionally, in packet-type transmission, information is sent to a transmission path at a frame rate. At this time, in order to improve the transmission quality,
Add a false 9 detection code. One of the methods is CR, C
There is a method.

Conventional transmission systems have drawbacks such as transmission efficiency, traffic non-uniformity, and line congestion. For this reason, a popular method is to divide the packet frame and transmit it in multiple channels for each channel, but the middle part of this method is the generation/inspection circuit for the chant detection code. A fist having this circuit for each grip channel has the disadvantage of increasing the number of circuit components.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, by providing an inspection function in the channel book, but by using a random access memory, the number of circuit parts can be reduced, and a simple control circuit can be added. generated in the frame by
Instead of checking after the end of the frame, ehc is calculated every time a divided frame block is received, and swAk is calculated when the end block of the frame is received.
The purpose of this invention is to provide a method for detecting i.

The error detection code generation/inspection method of the present invention includes a memory for C calculation, a register used for channel specification, a register to assist shift operations in memory cells, a register for outputting calculation results, and and a control circuit that controls the following.

It! of the present invention! The block structure of the 4C detection code generation/inspection method is shown in FIG. 1 is the CR of the received serial signal
A memory circuit for calculating C (IC) (1 address is assigned to this memory. The cell length of this memory (the number of bits corresponding to the address) is determined by the CRC generating polynomial. (For example, CC
(16 bits in case of ITT-CRC) Also, if the channel multiplicity of the received signal is n, this memory requires n cells. Therefore, if the generating polynomial is of degree m, the memory will be m×n bits. Functionally, this memory functions as a shift register within the cell. 2 is a register that holds an address for accessing this memory, and when a divided block of the i-th channel is received, the address of the memory allocated for it is loaded. 3 is a register necessary to perform a memory shift function. 4 is CI
This register is used to take out one shift from this memory when generating/inspecting LC.

5 is a logic circuit determined depending on the generating polynomial of C1 (, C, and consists of an exclusive OR circuit. 6 is a control circuit for controlling this circuit. 7 is an output circuit when CRC is added, and when detecting This is an output circuit for outputting detection results.

The details of this method will be explained based on a specific example of an actual journey. C
The generating polynomial of RC is X'+X+l.

A detailed circuit is shown in Fig. 2, and a time chart showing its operation is shown in Fig. 3. The helider part of the block is read from the manual data 101 and held in the register 122 via the bus 123 in the mezumink 209 . (In the figure, the block 9 that is held by the screen shows the contention of the i-channel.) The manual data is extracted from the memory R/W.
Clock 102 timing! Exclusive OR is performed with the data 103 outputted at -01 and stored in the register 105 at clock 104 (11). The value held in the register 108 of the memory 107 (i
) is applied to the first bit of the cell indicated by . During the next cycle 2040, this Δpi hated 1st shift is sent to the bus 109, and the 1st basket of No. Pass 11 (l
It is output to register 105 at timing 205, and is stored in register 10 of memory 107 at timing 206.
Fir:tA is applied to the second bit of cell (i) indicated by 3. Hereinafter, the above-mentioned operation is repeated for the 4 bits 6 of cell (i) at the data block at the end of the block shown at timing 210. At this time, the cell (i) IC retains red in the CRC calculation related to the data Q in it.

Then, block header h'19 (fj is this? Channel block 1 cock 1:, υ in register 108 becomes j at timing 211. Below, the same operation as i-channel is performed. I, cell (J) V?:, holds the CTGC total of 3I and 5 of j-chanol.When I receive the block of L 6 and i-channel shown at timing 212, the contents of the dip register +08 are changed to the timing 212. 2
] 3 becomes i, and the operation @simplified 7 is repeated from the previous 1 to 1 C calculation conclusion.

If this block is the end of the i-cha;noil frame, it is the 11 or crtc code of memory cell-1.

This negative value is loaded into the register 112 at timing 207 with pulse 111. On the other hand, the input data is input to the shift register 114 at the clock pulse 113, and is compared with the output 124 of the register 112 at the comparator 116. The output 117 of the comparator is stored in the 7-lip flop 119 at timing 208 by the bus 118, and the output value indicating the overload detection result is shifted by the clock 113 and output to the output IJ 121.

The method according to the invention allows CRC generation and checking with a small circuit and a simple control circuit in a system requiring split channel multiplexed transmission of frames. Also, in this method, the difference in the generator polynomial is only related to the length of the memory cell and the logic circuit. Also, the length of the received data is variable.

Even if the CRC rules (differences in generator polynomials) change for each channel, this can be handled by adding a simple logic circuit and a simple control circuit, providing great versatility.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating the invention in detail. FIG. 2 is a detailed circuit diagram illustrating the present invention in detail. Third
The figure is a timing diagram for explaining the detailed operation of the embodiment of the present invention. 1...Memory circuit, 2...Register, 3
...Register, 4...Register, 5.
...Logic circuit, 6...Control circuit, 7...
...output circuit. ,, ,/”-”1 Agent Patent attorney Hi Hara . 1st graduate

Claims (1)

[Claims] A code detection code generator/code generator that has a memory for CRCIL, a register used for channel specification, a register that assists shift operations in memory cells, a register that outputs calculation results, and a control circuit that controls these. Food inspection method.