JPS60115226A - Substrate temperature control method - Google Patents
Substrate temperature control methodInfo
- Publication number
- JPS60115226A JPS60115226A JP22204683A JP22204683A JPS60115226A JP S60115226 A JPS60115226 A JP S60115226A JP 22204683 A JP22204683 A JP 22204683A JP 22204683 A JP22204683 A JP 22204683A JP S60115226 A JPS60115226 A JP S60115226A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- lower electrode
- cooling gas
- back surface
- path
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 131
- 238000000034 method Methods 0.000 title claims description 32
- 239000000112 cooling gas Substances 0.000 claims abstract description 30
- 238000012545 processing Methods 0.000 claims abstract description 28
- 239000012212 insulator Substances 0.000 abstract description 18
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 abstract description 4
- 238000012546 transfer Methods 0.000 abstract description 2
- 239000002826 coolant Substances 0.000 abstract 4
- 239000007789 gas Substances 0.000 description 20
- 238000001179 sorption measurement Methods 0.000 description 17
- 239000003507 refrigerant Substances 0.000 description 14
- 230000000694 effects Effects 0.000 description 11
- 238000005530 etching Methods 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 238000001816 cooling Methods 0.000 description 7
- 238000007667 floating Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000003796 beauty Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の利用分野〕 一本発明は、基板の温度制御方法に関するものである。[Detailed description of the invention] [Field of application of the invention] The present invention relates to a method for controlling the temperature of a substrate.
基板を真空処理する装置、例えば、高周波放電を利用す
るドライエツチング装置の重要な用途の一つに半導体集
積回路等の微小固体素子の製造蟻こおける微細パターン
の形成がある。この微細ノ(ターンの形成においては、
通常、被加工物質の上iこ塗布したレジストと呼ばれる
高分子材料に紫外線を露光、現象して描いたパターンを
マスクとしてドライエツチングにより被加工物質に転写
することが行われている。One of the important uses of equipment for vacuum processing substrates, for example, dry etching equipment that utilizes high-frequency discharge, is the formation of fine patterns in the production of microscopic solid-state devices such as semiconductor integrated circuits. In the formation of this minute turn,
Usually, a pattern drawn by exposing a polymeric material called a resist coated on a material to be processed by ultraviolet rays and developing it is used as a mask and transferred to the material by dry etching.
しかしながら、プラズマとの化学反応熱やイオンまたは
電子などの衡撃入射エネルギ1こよりマスクおよび被加
工物質である基板が加熱されるため、十分な放熱が得ら
れない、即ち、基板の温度が良好に制御されない場合は
、マスクが変形、変質し正しいパターンが形成されな鳴
なったり、ドライエツチング後に残存するマスクの基板
力)らの除去が困難となる。そこで、これら不都合を排
除するだめの基板の温度制御方法は、従来より種々慣用
され提案されている。以下、これら従来の技術について
説明する。However, because the mask and the substrate, which is the material to be processed, are heated by the chemical reaction heat with the plasma and the balanced incident energy of ions or electrons, sufficient heat dissipation cannot be obtained, that is, the temperature of the substrate cannot be maintained properly. If this is not controlled, the mask will be deformed and altered, resulting in the inability to form a correct pattern and making it difficult to remove the mask's substrate force remaining after dry etching. Therefore, various substrate temperature control methods that eliminate these disadvantages have been conventionally used and proposed. These conventional techniques will be explained below.
従来技術の第1例としては、例えば、特公昭56−23
853号公報で示されている方法がある。A first example of the prior art is, for example, Japanese Patent Publication No. 56-23
There is a method disclosed in Japanese Patent No. 853.
浪
この方法は、高岡〆電源の出力が印加される基板台を水
冷し、該台上に被加工物質である基板を絶縁物を介して
載置し、電極に直流電圧を印加することでプラズマを介
して絶縁物に電位差を与え、これにより生じる静電吸着
力によつて基板を基板台に吸着させ、基板と基板台との
間の熱抵抗を減少させて基板を効果的に冷却するもので
ある。しかしながら、このような方法でも基板と絶縁物
との間の接触部分は少なく、微視的にみればわずかな隙
間を有している。また、この隙間には、プロセスガスが
入り込み、このガスは、熱抵抗となる。In Namiko's method, the substrate table to which the output of the Takaoka power supply is applied is water-cooled, the substrate to be processed is placed on the table via an insulator, and a DC voltage is applied to the electrodes to generate plasma. A device that applies a potential difference to the insulator through the insulator, and uses the resulting electrostatic adsorption force to attract the substrate to the substrate pedestal, reducing the thermal resistance between the substrate and the substrate pedestal and effectively cooling the substrate. It is. However, even with this method, there are only a few contact areas between the substrate and the insulator, and microscopically, there is a small gap. Further, a process gas enters this gap, and this gas acts as a thermal resistance.
一般にドライエツチング装置では、通常0. I To
rr程度のプロセスガス圧で基板はエツチング処理され
ており、基板と絶縁板との間の隙間は平均自由行路長よ
り小さ曵なるため、静電吸着力による隙間の減少は、熱
抵抗の点からはほとんど変わらず、接触面積が増加した
分だけ効果があがることになる。したがって、基板と基
板台との間の熱抵抗を減少させ基板をより効果的に冷却
するためには、大きな静電吸着力を必要とする。このた
め、このような方法では、次のような問題があった。In general, dry etching equipment usually uses 0. I To
The substrate is etched at a process gas pressure of about remains almost unchanged, and the effect increases as the contact area increases. Therefore, in order to reduce the thermal resistance between the substrate and the substrate stand and cool the substrate more effectively, a large electrostatic attraction force is required. Therefore, this method has the following problems.
(11基板が基板台から離脱しにくくなるため、エツチ
ング処理が終了した基板の搬送に時間を要したり、基板
をいためたりする。(11) It becomes difficult for the substrate to separate from the substrate stand, so it takes time to transport the substrate after the etching process, and the substrate may be damaged.
(2)・大きな静電吸着力を生じさせるには、絶縁物、
即−ち、基板に大きな電位差を与える必要があるが、し
かし、この電位差が太き畷なれば、基板内の素子に対す
るダメージが大きくなるため、集積回路の集積度が高ま
るにつれて要求が強ま゛っている薄いゲート膜の微細加
工では素子製作上のスループットが十分に得られない。(2)・Insulators,
In other words, it is necessary to apply a large potential difference to the substrate, but the larger the potential difference, the greater the damage to the elements within the substrate, so this requirement becomes stronger as the degree of integration of integrated circuits increases. The microfabrication of the thin gate film currently available does not provide sufficient throughput for device fabrication.
従来技術の第2例としては、例えば、特開昭57−14
5321号公報で示されているような方法がある。この
方法は、基板を気体ガスにより直接冷却するものである
。このような方法では、へリウムガス(以下、GH,と
略)のように熱伝導性の優れた冷却ガスを用いることで
、基板の冷却効率を向上させることができる。しかしな
がら、このような方法では、次のような欠点があった。As a second example of the prior art, for example, Japanese Patent Application Laid-Open No. 57-14
There is a method as shown in Japanese Patent No. 5321. In this method, the substrate is directly cooled by gas. In such a method, the cooling efficiency of the substrate can be improved by using a cooling gas with excellent thermal conductivity such as helium gas (hereinafter abbreviated as GH). However, such a method has the following drawbacks.
(1) 冷却ガスが基板の冷却面側にとどまらず真空処
理室内に多量に流れ込むため、GHeのように不活性ガ
スでもプロセスに与える影響は太き(、したがって、全
てのプロセスに使用することができない。(1) Since the cooling gas does not stay on the cooling surface side of the substrate but flows in large quantities into the vacuum processing chamber, even an inert gas like GHe has a large effect on the process (therefore, it cannot be used in all processes. Can not.
従来技術の第3例としては、例えば、E、 J。As a third example of the prior art, for example, E, J.
Egerton他、 5olid 8tate Tec
hnology、 Vol、 25゜48、P84〜8
7(1982−8)で示されているような方法がある。Egerton et al., 5solid 8tate Tec
hnology, Vol, 25°48, P84-8
7 (1982-8).
この方法は、水冷された基板台とこの基板台に載置され
クランプで外周辺を固定された基板との間に圧力が6
TOrr 程度のGHeを流通させて電極と基板との間
の熱抵抗を減少させ、これにより基板を効果的に冷却す
るものである。しかしながら、このような方法でもGH
。In this method, pressure is applied between the water-cooled substrate table and the substrate placed on the substrate table and secured around the outside with clamps.
The thermal resistance between the electrode and the substrate is reduced by circulating GHe of about 1 Torr, thereby effectively cooling the substrate. However, even with this method, GH
.
の真空処理室内への流出は避けられず、したがって上記
した従来技術の第2例での問題点と同様の問題点を有し
、更に次のような問題点をも有している。The outflow into the vacuum processing chamber is unavoidable, and therefore there are problems similar to those in the second example of the prior art described above, and the following problems also occur.
(1) 基板の基板台からの浮上り防止用として基板の
外周辺を固定するクランプが設けられており。(1) A clamp is provided to secure the outer periphery of the board to prevent the board from floating up from the board stand.
このため、基板内の素子製作面積が減少すると共に、基
板搬送が極めて複雑となり、その結果、装置が大型化す
ると共に信頼性が低下する。Therefore, the area for fabricating elements within the substrate is reduced, and the transportation of the substrate becomes extremely complicated, resulting in an increase in the size of the device and a decrease in reliability.
(2)基板の裏面と基板台との間の隙間にGHeが偏在
する。゛
〔発明の目的〕
本発明の目的は、基板搬送が容易でプロセスに与える影
響を少なくできる基板の温度制御方法を提供するもので
ある。(2) GHe is unevenly distributed in the gap between the back surface of the substrate and the substrate stand. [Object of the Invention] An object of the present invention is to provide a method for controlling the temperature of a substrate, which allows easy transportation of the substrate and reduces the influence on the process.
本発明は、真空処理される基板の少なくとも外周辺を冷
却される基板台に吸着させると共優こ、基板台との間の
隙−に冷却ガスを満たすことで、機械的クランプ手段を
不用とし、かつ、吸着力を極力小さ鳴すると共に冷却ガ
スの真空処理室内への流出を抑制しようとしたものであ
るO
〔発明の実施例〕
本発明の一実施例を第1図により説明する。The present invention is advantageous in that at least the outer periphery of a substrate to be vacuum-processed is adsorbed to a substrate stand to be cooled, and the gap between the substrate and the substrate stand is filled with cooling gas, thereby eliminating the need for mechanical clamping means. , and attempts to suppress the outflow of the cooling gas into the vacuum processing chamber while minimizing the adsorption force. [Embodiment of the Invention] An embodiment of the present invention will be described with reference to FIG. 1.
第1図は、本発明を実施したドライエツチング装置の一
例を示すもので、真空処理室10の底壁には、絶縁体1
1を介して基板台である下部電極Iが電気絶縁され、か
つ、気密に設けられている。下部電極前と放電空間園を
有し上下方向に対向して上部電極前が真空処理室10に
内設されている。FIG. 1 shows an example of a dry etching apparatus embodying the present invention.
A lower electrode I, which is a substrate stand, is electrically insulated and airtightly provided via the substrate 1. A vacuum processing chamber 10 is provided with the front of the lower electrode and the discharge space, and the front of the upper electrode is vertically opposed to each other.
載置される基板間の裏面の少なくとも外周辺に対応して
絶縁物印が下部電極前の表面に埋設され、絶縁物加の内
側の下部電極列には、基板間が載置されていない場合、
放電空間蕊と連通する溝21が形成されている。また、
冷媒流路囚が、n421の下方位置で下部電極前に形成
されている。また、下部電極前には溝21と連通して冷
却ガス供給路23aと冷却ガス排出路23bとが、冷媒
流路nと連通して冷媒供給路24gと冷媒排出路24b
とがそれぞれ形成されている。冷却ガス供給路23gに
は、冷却ガス源(図示省略)に連結された導管70 a
が連結され、冷却ガス排出路23bには、導管70 b
の一端が連結されている。導管70 aには、マスフロ
ーコントローラ(以下%MFCと略)nが設けられ、結
する排気用の導管戎に合流連結されている。冷媒供給路
24gには、冷媒源(図示省略)に連結された導管90
aが連結され、冷媒排出路24bには、冷媒排出用の導
管90bが連結されている。下部電極前には、マツチン
グボックス100を介して高周波電源iotが接続され
ると共に、高周波しゃ断回路102を介して直流電源1
03が接続されている。When an insulator mark is embedded in the surface in front of the lower electrode corresponding to at least the outer periphery of the back surface between the substrates to be placed, and no part of the substrate is placed on the lower electrode row inside the insulator mark. ,
A groove 21 communicating with the discharge space is formed. Also,
A refrigerant flow path is formed in front of the lower electrode at a position below n421. Further, in front of the lower electrode, a cooling gas supply path 23a and a cooling gas discharge path 23b are connected to the groove 21, and a refrigerant supply path 24g and a refrigerant discharge path 24b are connected to the refrigerant flow path n.
are formed respectively. The cooling gas supply path 23g includes a conduit 70a connected to a cooling gas source (not shown).
A conduit 70b is connected to the cooling gas discharge path 23b.
One end of is connected. The conduit 70a is provided with a mass flow controller (hereinafter abbreviated as %MFC) n, and is connected to a conduit pipe for exhaust gas connected to the conduit 70a. The refrigerant supply path 24g includes a conduit 90 connected to a refrigerant source (not shown).
A is connected to the refrigerant discharge path 24b, and a refrigerant discharge conduit 90b is connected to the refrigerant discharge path 24b. In front of the lower electrode, a high frequency power supply IOT is connected via a matching box 100, and a DC power supply 1 is connected via a high frequency cutoff circuit 102.
03 is connected.
また、上部電極前には、放電空間(9)に開口するガス
放出孔(図示省略)とガス放出孔と連通するガス流通M
(図示省略)とが形成され、ガス流通路には、処理ガス
供給装置(図示省略)に連結された導管(図示省略)が
連結されている。なお、真空処理室10.高周波電源1
01.直流電源103はそれぞれ接地されている。In addition, in front of the upper electrode, there is a gas discharge hole (not shown) that opens into the discharge space (9) and a gas flow M that communicates with the gas discharge hole.
(not shown) is formed, and a conduit (not shown) connected to a processing gas supply device (not shown) is connected to the gas flow path. Note that the vacuum processing chamber 10. High frequency power supply 1
01. The DC power supplies 103 are each grounded.
ここで、溝乙の深さは、冷却ガスの基板間の裏面と下部
電極加、即ち、溝ガ並びに絶縁物ωとの間の隙間での偏
在を防止するために、静電吸着力による基板間の下部電
極筒への吸着時に基板(資)の裏面と溝21の底面との
間の隙間が基板間の裏面と絶縁物ωとの間の隙間より太
き曵なるよう響こ選定する。更に、吸着時の基板間の裏
面と溝21の底面との間の隙間が冷却ガスの平均自由行
路長以下畳こなれば冷却ガスの伝熱効果が低下するよう
毫こなるため、吸着時の基板間の裏面と溝21の底面と
の間の隙間が基板間の裏面と絶縁物ωとの間の隙間以上
、好まし曵は、冷却ガスの平均自由行路長以下となるよ
うに溝4の深さを選定する。また、基板間の裏面で絶縁
物ωに吸着される部分(以下、吸着部と略)の面積は、
冷却ガスのガス圧と真空処理室10の圧力との差圧によ
る基板間の下部電極前からの浮上りを防止するために冷
却ガスのガス圧と真空処理室10の圧力との差圧により
決まる必要静電吸着力により選定する。例えば、冷却ガ
スの圧力がITorrで真空処理室10の圧力が0.1
Torrの場合、基板間の下部型i#加からの浮上IJ
を防止するための必要静電吸着力は約1.3 f /c
tAであり、これより吸着部の面積は基板間の裏面面積
の約1に選定される。Here, the depth of the groove O is set to prevent the cooling gas from being unevenly distributed in the gap between the back surface of the substrate and the lower electrode, that is, between the groove and the insulator ω. The gap between the back surface of the substrate (material) and the bottom surface of the groove 21 is selected to be larger than the gap between the back surface of the substrate and the insulator ω when adsorbed to the lower electrode tube between the substrates. Furthermore, if the gap between the back surface between the substrates and the bottom surface of the groove 21 during adsorption is less than the mean free path length of the cooling gas, the heat transfer effect of the cooling gas will be reduced. The depth of the groove 4 is such that the gap between the back surface of the substrate and the bottom surface of the groove 21 is greater than the gap between the back surface of the substrate and the insulator ω, and preferably the depth is less than or equal to the mean free path length of the cooling gas. Select the In addition, the area of the part (hereinafter abbreviated as the adsorption part) that is adsorbed by the insulator ω on the back surface between the substrates is:
It is determined by the differential pressure between the cooling gas and the vacuum processing chamber 10 in order to prevent the substrates from floating from in front of the lower electrode due to the differential pressure between the cooling gas and the vacuum processing chamber 10. Select based on the required electrostatic adsorption force. For example, when the pressure of the cooling gas is ITorr and the pressure of the vacuum processing chamber 10 is 0.1
In the case of Torr, the floating IJ from the lower type i# addition between the substrates
The required electrostatic adsorption force to prevent this is approximately 1.3 f/c
tA, and from this, the area of the suction portion is selected to be approximately 1 of the area of the back surface between the substrates.
第1図の下部電極の詳細構造例を@2図、第3図により
説明する。A detailed structural example of the lower electrode shown in FIG. 1 will be explained with reference to FIGS. 2 and 3.
第2図、@3図で、冷却ガス供給路Z3 a 1.t
、この場合、導管25aで形成され、導管25aは、こ
の場合、下部電極前の基板載置位置中心を軸心として上
下動可能に設けられている。導管5aの外側には冷却ガ
ス排出路23bを形成して導管25bが配設され導管2
5bの外側には、冷媒供給路24aを形成して導管25
cが配設され、導管25cの外側には、冷媒排出路24
bを形成して導管25dが配設されている。導管25b
の上端は、電極上板かに設けられ、電極上板部とその下
方の電極上板部がと導管25bの上端部とで空室公が形
成されている。空室路には、分割板四が冷媒流路nを形
成して内設され、導管25cのユ端は、分割板四に、ま
た、導管25dの上端は、電極上板部nに設けられてい
る。基板(図示省略)が載置される電極上板がの表面に
は、この場合、放射状の渭21 aと円周状のWI21
bとが複数条形成されている。溝21g、21bは、導
管5a、25bと勿論連通している。基板が載置される
面で、溝21a、21bが形成されていない電極上板が
の表面には、絶縁膜(図示省略)がコーチイブされてい
る。ここで、溝21a、21bの深さは、第1図の清4
の深さと同様に選定されている。また、吸着部は溝21
a、21bで分割されているが、その面積は勿論冷却ガ
スによる基板間の下部電極旬からの浮上り防止に必要な
面積に選定されている。In Figures 2 and 3, cooling gas supply path Z3 a 1. t
In this case, it is formed of a conduit 25a, and in this case, the conduit 25a is provided so as to be movable up and down about the center of the substrate placement position in front of the lower electrode. A cooling gas discharge path 23b is formed outside the conduit 5a, and a conduit 25b is provided.
5b, a refrigerant supply path 24a is formed and a conduit 25 is formed.
A refrigerant discharge passage 24 is provided outside the conduit 25c.
A conduit 25d is disposed forming the b. Conduit 25b
The upper end is provided on the electrode upper plate, and a space is formed between the electrode upper plate portion, the electrode upper plate portion below the electrode upper plate portion, and the upper end portion of the conduit 25b. A dividing plate 4 is installed in the empty chamber path to form a refrigerant flow path n, and the end of the conduit 25c is installed in the dividing plate 4, and the upper end of the conduit 25d is installed in the electrode upper plate part n. ing. In this case, the surface of the electrode upper plate on which the substrate (not shown) is placed has a radial wave 21a and a circumferential WI21.
A plurality of strips are formed. The grooves 21g, 21b are of course in communication with the conduits 5a, 25b. An insulating film (not shown) is coated on the surface of the electrode upper plate on which the substrate is placed and where the grooves 21a and 21b are not formed. Here, the depth of the grooves 21a and 21b is as shown in FIG.
The depth has been selected as well. In addition, the suction part is the groove 21
It is divided into sections a and 21b, and the area is of course selected to be an area necessary to prevent the cooling gas from floating up from the bottom electrode between the substrates.
なお、第2図、第3図で、110は基板が載置されない
電極上板々の表面を保護する電極カバーで、111は下
部電極蜀の電極上板々の表面以外を保護する絶縁カバ、
112はシールド板である。また、導管25aの上端に
は、電極上板部への基板の載置時並びに電極上板部から
の基板の離脱時に基板を支持する爪113が、この場合
、3本120度間隔にて配設されている。In addition, in FIGS. 2 and 3, 110 is an electrode cover that protects the surface of the electrode upper plates on which the substrate is not placed, 111 is an insulating cover that protects the lower electrode other than the surface of the electrode upper plates,
112 is a shield plate. Furthermore, at the upper end of the conduit 25a, three claws 113 are arranged at 120 degree intervals to support the substrate when the substrate is placed on the electrode upper plate and when the substrate is removed from the electrode upper plate. It is set up.
第1図で、基板間が公知の搬送装置(図示省略)により
真空処理室lOに搬入され、その裏面外周辺部を絶縁物
ωと対応させて下部電極前に載置される。、下部電極前
への基板間の載置完了後、処理ガス供給装置から導管を
経メガス流通路に供給された処理ガスが、ガス流通路を
流通した後にガス放出孔より放電空間(資)に放出され
る。これと共に下部電極蜀には高周波電源101より高
周波電力が印加されて下部型!#i美と上部電極恥との
間にはグロー放電が生じる。このグロー放電によりプラ
ズマが発生してエツチングが開始されると、基板間は、
絶縁物ωの両端にかかる電位差により生じる静電吸着力
で下部電極前に吸着される。その後、溝21には、冷却
ガス源より冷却ガス、例えば、GH,が供給され、冷媒
流路nを流通する冷媒、例えば、水で冷却されている下
部電極前と基板間との熱抵抗を減少させることにより基
板間は効果的に冷却される0エツチングの終了に近づく
と、溝21へのGHaの供給は停止され、エツチングの
終了に伴って、放電空間刃への処理ガスの放出、下部電
極旬への高周波電力および直流電圧の印加が停止される
。その後、引続き基板間に生じている静電吸着力は解除
され、基板間は、公知の搬送装置によす下部型f!旬よ
り除去されて真空処理室10から搬出される。In FIG. 1, the substrates are transported into a vacuum processing chamber IO by a known transport device (not shown), and placed in front of the lower electrode with the outer periphery of the back surface corresponding to the insulator ω. After the completion of placing the substrates in front of the lower electrode, the processing gas is supplied from the processing gas supply device to the mega gas flow passage through the conduit, and after flowing through the gas flow passage, enters the discharge space from the gas discharge hole. released. At the same time, high-frequency power is applied from the high-frequency power source 101 to the lower electrode Shu, and the lower electrode is connected! A glow discharge occurs between #i beauty and the upper electrode shame. When plasma is generated by this glow discharge and etching begins, the gap between the substrates is
The insulator ω is attracted in front of the lower electrode by the electrostatic attraction force generated by the potential difference applied to both ends of the insulator ω. Thereafter, a cooling gas such as GH is supplied from a cooling gas source to the groove 21 to reduce the thermal resistance between the substrate and the front of the lower electrode, which is cooled by a refrigerant, such as water, flowing through the refrigerant flow path n. By reducing etching, the space between the substrates is effectively cooled. 0 When the end of etching approaches, the supply of GHa to the groove 21 is stopped, and as the etching ends, the processing gas is released to the discharge space blade, and the lower part Application of high frequency power and DC voltage to the electrodes is stopped. Thereafter, the electrostatic attraction force that continues to be generated between the substrates is released, and the lower mold f! It is removed from the top and carried out from the vacuum processing chamber 10.
本実施例のような基板の温度制御方法では、次のような
効果が得られる。The substrate temperature control method as in this embodiment provides the following effects.
11)基板と下部電極とにおける熱抵抗を熱伝導性の良
いGHeにより低下させているので、基板の冷却効果が
著しいと共に、従来の静電吸着により基板と下部電極と
の接触面積を増加させて熱抵抗を減少させる方法と比較
すると、静電吸着力の大きさはGHt+の圧力と真空処
理室の圧力との圧力差による基板の浮き上りを防止する
のに必要な大きさで良<、 、 GH,の圧力とプラズ
マの圧力との圧力差を熱抵抗の許す範囲で小さくするこ
とにより静電吸着力を小さくしても基板冷却の効果が十
分得られる。11) Since the thermal resistance between the substrate and the lower electrode is lowered by GHe, which has good thermal conductivity, the effect of cooling the substrate is remarkable, and the contact area between the substrate and the lower electrode is increased by conventional electrostatic adsorption. Compared to the method of reducing thermal resistance, the electrostatic adsorption force can be as large as necessary to prevent the substrate from lifting due to the pressure difference between the GHt+ pressure and the vacuum processing chamber pressure. By reducing the pressure difference between the pressure of GH and the plasma pressure within the range allowed by thermal resistance, a sufficient substrate cooling effect can be obtained even if the electrostatic adsorption force is reduced.
(2)静電吸着力が小さいため、基板の下部電極からの
離脱が容易となり、エツチング処理が終了した基板の搬
送時間を短縮できると共に、基板の損傷を防止できる。(2) Since the electrostatic adsorption force is small, the substrate can be easily separated from the lower electrode, and the time for transporting the substrate after etching can be shortened, and damage to the substrate can be prevented.
(3) 静電吸着力が小さくてよいため、基板に与えら
れる電位差は小さく基板内の素子に対するダメージを小
さくできる。したがって、薄いゲート膜の微細加工でも
素子製作上のスループットが十分に得られる。(3) Since the electrostatic adsorption force may be small, the potential difference applied to the substrate is small and damage to elements within the substrate can be reduced. Therefore, even with fine processing of a thin gate film, a sufficient throughput in device fabrication can be obtained.
(4)冷却ガスであるGH,は吸着部で真空処理室内へ
の流出を抑制されるため、Gl(eのプロセスに与える
影響は少なくなり、全てのプロセスに使用することがで
きる。(4) Since GH, which is a cooling gas, is suppressed from flowing into the vacuum processing chamber at the adsorption part, its influence on the process of Gl(e) is reduced, and it can be used in all processes.
(5)基板の下部電極からの浮上りを機械的クランプ手
段によらず静電吸着力の付与で防止しているため、基板
内の素子製作面積の減少を防止で−きると共に、基板搬
送を容易化でき、その結果、装置の大型化を抑制できる
と共に信頼性を向上できる。(5) Since the floating of the substrate from the lower electrode is prevented by applying electrostatic adsorption force without using mechanical clamping means, it is possible to prevent a reduction in the area for manufacturing elements on the substrate, and to facilitate substrate transportation. As a result, it is possible to suppress the increase in size of the device and improve reliability.
(6) 基板の裏面と下部電極との間の隙間でのGHe
の偏在を防止できる。(6) GHe in the gap between the back surface of the substrate and the lower electrode
can prevent uneven distribution of
173 GH,を供給するMFCをプロセス制御コンピ
ュータと結合することで、あらかじめめた基板の温度と
GH,の供給量との間の関係からGHeの供給量を制御
することにより基板の温度な−定の温度に保持できる。By connecting an MFC that supplies 173 GH, with a process control computer, the supply amount of GHe can be controlled based on the relationship between the predetermined substrate temperature and the supply amount of GH, and the temperature of the substrate can be kept constant. Can be maintained at a temperature of
このような制御は、fvl−Cu −81材のドライエ
ツチングの際に特に有効であり、ホトレジストがダメー
ジを受けない範囲の高い温度に制御して被エツチング材
の残渣を減少させることができる。Such control is particularly effective when dry etching fvl-Cu-81 material, and can reduce the residue of the material to be etched by controlling the temperature to a high temperature within a range that does not damage the photoresist.
(8)プラズマの圧力が高い場合には、エツチング速度
が基板の温度上昇に伴って増加するプロセスもあり、こ
のような場合には、基板の温度があらかしめ設定した一
定温度を越えた場合に、GH,を流して冷却効果を上げ
ホトレジストのダメージを防止しながらエツチング時間
の短縮を図ることができる。(8) When the plasma pressure is high, there are processes in which the etching rate increases as the substrate temperature rises. In such cases, when the substrate temperature exceeds a preset constant temperature, , GH, can be flowed to increase the cooling effect and reduce the etching time while preventing damage to the photoresist.
第4図は、本発明を実施したドライエツチング装置の他
の例を示すもので、真空処理室10の頂壁と上部型′!
f!旬には、真空処理室10外部と放電空間部とを連通
して光路120が形成され、光路120の真空処理室1
0外部側には、透光窓121が気密に設けられている。FIG. 4 shows another example of a dry etching apparatus embodying the present invention.
f! During the period, an optical path 120 is formed by communicating the outside of the vacuum processing chamber 10 and the discharge space, and the optical path 120 communicates with the outside of the vacuum processing chamber 1 and the discharge space.
A transparent window 121 is airtightly provided on the outside side.
透光窓121と対応する真空処理室10外部には、温度
計測手段、例えば、赤外線温度゛計122が設けられて
いる。赤外線温度122の出力はアンプ123を介して
プロセス制御用コンピュータ124に入力され、プロセ
ス制御用コンピュータ!24により演算された指令信号
がNFC71に入力されるようになっている。なお、そ
の他、第1図と同−装置等は、同一符号で示し説明を省
略する。Temperature measuring means, for example, an infrared thermometer 122, is provided outside the vacuum processing chamber 10 corresponding to the transparent window 121. The output of the infrared temperature 122 is input to the process control computer 124 via the amplifier 123. The command signal calculated by 24 is input to the NFC 71. In addition, the same devices and the like as in FIG. 1 are indicated by the same reference numerals, and the description thereof will be omitted.
本実施例のような基板の温度制御方法では、更に次のよ
うな効果が得られる。The substrate temperature control method as in this embodiment further provides the following effects.
(1)基板の温度を計測しなからGHeの供給量を調整
して基板の温度を制御することができる。(1) The temperature of the substrate can be controlled by adjusting the supply amount of GHe without measuring the temperature of the substrate.
以上説明した実施例では、基板の吸着に静電吸着力を用
いているが、プラズマガスの圧力が高いプロセスにおい
ては真空吸着力を用いることも可能である。また、絶縁
物下面に正極と負極とを交互に並べて配置し静電吸着力
を基板に付与するようにしても良い。また、下地の材料
が露出し始めてから更にオーバーエツチングを行うよう
な場合は、下地の材料が露出し始めた時点でG Heの
供給を停止し下部電極に直流電圧を逆印加するようにす
る。このようにすれば、エツチング修了時点での基板に
残留する静電力を更に減少させることができるため、基
板搬出時に基板を損傷させることがなζ、基板搬出に要
する時間を短縮する=とができる。但し、この場合は、
エツチング中の基板ノfi度をオーバーエツチング時の
温度上昇分だけ下げてお曵よう制御してやる必要がある
。また、冷却、ガスとしてGHeの他に水素ガス、ネオ
ンガス等の熱伝導性の良いガスを用いても良い。In the embodiments described above, electrostatic adsorption force is used to adsorb the substrate, but vacuum adsorption force can also be used in processes where the pressure of plasma gas is high. Alternatively, positive electrodes and negative electrodes may be arranged alternately on the lower surface of the insulator to apply electrostatic adsorption force to the substrate. In addition, if overetching is to be performed after the underlying material begins to be exposed, the supply of G He is stopped and the DC voltage is reversely applied to the lower electrode when the underlying material begins to be exposed. In this way, the electrostatic force remaining on the substrate at the end of etching can be further reduced, so the substrate will not be damaged when unloading the substrate, and the time required for unloading the substrate can be shortened. . However, in this case,
It is necessary to control the temperature of the substrate during etching by lowering it by the amount of temperature rise during over-etching. Further, as the cooling gas, a gas having good thermal conductivity such as hydrogen gas or neon gas may be used in addition to GHe.
なお1本発明は、その他の冷却される基板台に載置保持
されて真空処理される基板の温度を制御するのに同様の
効果を有する。Note that the present invention has a similar effect when controlling the temperature of a substrate placed and held on another substrate stand to be cooled and subjected to vacuum processing.
本発明は、以上説明し・た、よう1こ、真空処理される
基板の少な曵とも外周辺を冷却される基板台に吸着させ
ると共に、基板の裏面と基板台との間の隙間に冷却ガス
を満たすことで、機械的クランプ手段が不用、かつ、吸
着力を必要最小限度に小さくできると共に冷却ガスの真
空処理室内への流出を抑制できるので、基板搬送が容易
でプロセスに与える影響を少な曵できるという効果があ
る0As described above, the present invention has the following advantages: At least the outer periphery of a substrate to be vacuum processed is adsorbed to a substrate stand to be cooled, and cooling gas is supplied to the gap between the back surface of the substrate and the substrate stand. By satisfying the above requirements, mechanical clamping means are not required, the adsorption force can be reduced to the minimum necessary, and the outflow of cooling gas into the vacuum processing chamber can be suppressed, making it easy to transport substrates and minimizing the impact on the process. It has the effect of being able to do it0
第1図は、本発明を実施したドライエツチング装置の一
例を示す構成図、第2図は、第1図の下部電極の詳細平
面図、第3図は、第2図のA−A視断面図、第4図は、
本発明を実施したドライエツチング装置の他の例を示す
構成図である。
10・・・・・・真空処理室、加・・・・・・下部電極
、21,21a。FIG. 1 is a configuration diagram showing an example of a dry etching apparatus embodying the present invention, FIG. 2 is a detailed plan view of the lower electrode in FIG. 1, and FIG. 3 is a cross-sectional view taken along line AA in FIG. Figure 4 is
FIG. 3 is a configuration diagram showing another example of a dry etching apparatus embodying the present invention. 10... Vacuum processing chamber, processing... Lower electrode, 21, 21a.
Claims (1)
る基板の温度を制御する方法において、前記基板の裏面
の少なくとも外周辺を前記基板台に吸着させると共に、
基板の裏面と基板台との間の隙間に冷却ガスを満たすこ
とを特徴とする基板の温度制御方法。 2、前記基板の裏面の少な曵とも外周辺を前記基板台に
静電吸着させる特許請求の範囲第1項記戦の基板のへ温
度制御方法。 3、前記基板の前記基板台に吸着された裏面を除く裏面
と基板台との間の隙間を基板の基板台に吸着された裏面
と基板台との間の隙間以上、好まし曵は、前記冷却ガス
の平均自由行路長以下とする特許請求の範囲第1項又は
第2項記載の基板の温度制御方法。[Claims] 1. A method for controlling the temperature of a substrate placed and held on a cooled substrate stand to be subjected to vacuum processing, comprising: adsorbing at least the outer periphery of the back surface of the substrate to the substrate stand;
A method for controlling the temperature of a substrate, characterized by filling a gap between the back surface of the substrate and a substrate stand with cooling gas. 2. The temperature control method for a substrate according to claim 1, wherein at least the outer periphery of the back surface of the substrate is electrostatically attracted to the substrate stand. 3. Preferably, the gap between the back surface of the substrate other than the back surface adsorbed on the substrate stand and the substrate stand is equal to or larger than the gap between the back surface of the substrate adsorbed on the substrate stand and the substrate stand. 3. The method of controlling the temperature of a substrate according to claim 1 or 2, wherein the mean free path length of the cooling gas is equal to or less than the mean free path length of the cooling gas.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58222046A JPH0622213B2 (en) | 1983-11-28 | 1983-11-28 | Sample temperature control method and apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58222046A JPH0622213B2 (en) | 1983-11-28 | 1983-11-28 | Sample temperature control method and apparatus |
Related Child Applications (8)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1249149A Division JP2580791B2 (en) | 1989-09-27 | 1989-09-27 | Vacuum processing equipment |
JP1249150A Division JPH0670984B2 (en) | 1989-09-27 | 1989-09-27 | Sample temperature control method and apparatus |
JP1249151A Division JPH0670985B2 (en) | 1989-09-27 | 1989-09-27 | Sample temperature control method and apparatus |
JP1249152A Division JPH0670986B2 (en) | 1989-09-27 | 1989-09-27 | Vacuum processing equipment sample holding method |
JP5078095A Division JP2636781B2 (en) | 1995-03-10 | 1995-03-10 | Vacuum processing method |
JP5077995A Division JP2626618B2 (en) | 1995-03-10 | 1995-03-10 | Sample holding method for vacuum processing equipment |
JP5078395A Division JP2636782B2 (en) | 1995-03-10 | 1995-03-10 | Control method of heat transfer gas for sample temperature control |
JP5078195A Division JP2679667B2 (en) | 1995-03-10 | 1995-03-10 | Vacuum processing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60115226A true JPS60115226A (en) | 1985-06-21 |
JPH0622213B2 JPH0622213B2 (en) | 1994-03-23 |
Family
ID=16776242
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58222046A Expired - Lifetime JPH0622213B2 (en) | 1983-11-28 | 1983-11-28 | Sample temperature control method and apparatus |
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JP (1) | JPH0622213B2 (en) |
Cited By (15)
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JPS63141317A (en) * | 1986-12-03 | 1988-06-13 | Mitsubishi Electric Corp | Etching treatment device |
JPS63274147A (en) * | 1987-05-06 | 1988-11-11 | Hitachi Ltd | Dry etching |
JPH01298721A (en) * | 1988-05-27 | 1989-12-01 | Tokuda Seisakusho Ltd | Vacuum processor |
JPH029120A (en) * | 1988-06-28 | 1990-01-12 | Tokuda Seisakusho Ltd | Vacuum processor |
JPH0230128A (en) * | 1988-05-18 | 1990-01-31 | Veeco Instr Inc | Method of transferring and cooling substrate and apparatus for executing the method |
JPH02110925A (en) * | 1989-09-27 | 1990-04-24 | Hitachi Ltd | Vacuum processing equipment |
JPH02210826A (en) * | 1989-02-10 | 1990-08-22 | Hitachi Ltd | Plasma etching method and equipment |
JPH02120832U (en) * | 1989-03-15 | 1990-09-28 | ||
JPH0393226A (en) * | 1989-09-05 | 1991-04-18 | Iwatani Internatl Corp | Wafer cooler in wafer dry etching system |
JPH03104887A (en) * | 1989-09-20 | 1991-05-01 | Hitachi Ltd | Vacuum treating device |
JPH0373453U (en) * | 1989-11-22 | 1991-07-24 | ||
US5609689A (en) * | 1995-06-09 | 1997-03-11 | Tokyo Electron Limited | Vacuum process apparaus |
JP2007201355A (en) * | 2006-01-30 | 2007-08-09 | Hitachi High-Technologies Corp | Wafer mounting electrode |
WO2014097520A1 (en) * | 2012-12-20 | 2014-06-26 | キヤノンアネルバ株式会社 | Oxidation treatment device, oxidation method, and method for producing electronic device |
CN113053715A (en) * | 2019-12-27 | 2021-06-29 | 中微半导体设备(上海)股份有限公司 | Lower electrode assembly, plasma processing device and working method thereof |
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JP6723660B2 (en) | 2017-03-24 | 2020-07-15 | 住友重機械イオンテクノロジー株式会社 | Wafer holding device and wafer attaching/detaching method |
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---|---|---|---|---|
JPS55115047U (en) * | 1979-02-06 | 1980-08-13 | ||
JPS5832410A (en) * | 1981-08-06 | 1983-02-25 | ザ・パ−キン−エルマ−・コ−ポレイシヨン | Method and device for treating structure under gas reduced pressure environment |
JPS58132937A (en) * | 1982-01-29 | 1983-08-08 | バリアン・アソシエイツ・インコ−ポレイテツド | Semiconductor wafer heat treating device by gas conductor associated with gas inlet in environment |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63141317A (en) * | 1986-12-03 | 1988-06-13 | Mitsubishi Electric Corp | Etching treatment device |
JPS63274147A (en) * | 1987-05-06 | 1988-11-11 | Hitachi Ltd | Dry etching |
JPH0230128A (en) * | 1988-05-18 | 1990-01-31 | Veeco Instr Inc | Method of transferring and cooling substrate and apparatus for executing the method |
JPH01298721A (en) * | 1988-05-27 | 1989-12-01 | Tokuda Seisakusho Ltd | Vacuum processor |
JPH029120A (en) * | 1988-06-28 | 1990-01-12 | Tokuda Seisakusho Ltd | Vacuum processor |
JPH02210826A (en) * | 1989-02-10 | 1990-08-22 | Hitachi Ltd | Plasma etching method and equipment |
JPH02120832U (en) * | 1989-03-15 | 1990-09-28 | ||
JPH0393226A (en) * | 1989-09-05 | 1991-04-18 | Iwatani Internatl Corp | Wafer cooler in wafer dry etching system |
JPH03104887A (en) * | 1989-09-20 | 1991-05-01 | Hitachi Ltd | Vacuum treating device |
JPH02110925A (en) * | 1989-09-27 | 1990-04-24 | Hitachi Ltd | Vacuum processing equipment |
JPH0373453U (en) * | 1989-11-22 | 1991-07-24 | ||
US5609689A (en) * | 1995-06-09 | 1997-03-11 | Tokyo Electron Limited | Vacuum process apparaus |
JP2007201355A (en) * | 2006-01-30 | 2007-08-09 | Hitachi High-Technologies Corp | Wafer mounting electrode |
JP4611217B2 (en) * | 2006-01-30 | 2011-01-12 | 株式会社日立ハイテクノロジーズ | Wafer mounting electrode |
WO2014097520A1 (en) * | 2012-12-20 | 2014-06-26 | キヤノンアネルバ株式会社 | Oxidation treatment device, oxidation method, and method for producing electronic device |
JP6016946B2 (en) * | 2012-12-20 | 2016-10-26 | キヤノンアネルバ株式会社 | Oxidation treatment apparatus, oxidation method, and electronic device manufacturing method |
JPWO2014097520A1 (en) * | 2012-12-20 | 2017-01-12 | キヤノンアネルバ株式会社 | Oxidation treatment apparatus, oxidation method, and electronic device manufacturing method |
US9905441B2 (en) | 2012-12-20 | 2018-02-27 | Canon Anelva Corporation | Oxidation process apparatus, oxidation method, and method for manufacturing electronic device |
CN113053715A (en) * | 2019-12-27 | 2021-06-29 | 中微半导体设备(上海)股份有限公司 | Lower electrode assembly, plasma processing device and working method thereof |
CN113053715B (en) * | 2019-12-27 | 2023-03-31 | 中微半导体设备(上海)股份有限公司 | Lower electrode assembly, plasma processing device and working method thereof |
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JPH0622213B2 (en) | 1994-03-23 |
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