JPS6010647A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS6010647A JPS6010647A JP58119215A JP11921583A JPS6010647A JP S6010647 A JPS6010647 A JP S6010647A JP 58119215 A JP58119215 A JP 58119215A JP 11921583 A JP11921583 A JP 11921583A JP S6010647 A JPS6010647 A JP S6010647A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- integrated circuit
- hybrid integrated
- sheets
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims abstract description 37
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000007789 sealing Methods 0.000 claims abstract description 8
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 239000003990 capacitor Substances 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 238000010304 firing Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、セラミック積層配線基板を使用した混成集積
回路装置に係り、特に部品搭載部をくり抜いたアルミナ
グリーンシートと、封止用セラミック蓋の部分をくシ抜
いたアルミナグリーンシートとを積層して、部品を基板
内部に格納し、次に、平板状セラミック蓋を基板の封止
部分にはめ込んで樹脂封止した超薄型化が可能で高信頼
度の混成集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a hybrid integrated circuit device using a ceramic laminated wiring board, and in particular, an alumina green sheet with a hollowed out component mounting area and an alumina green sheet with a hollowed out ceramic lid for sealing. A highly reliable hybrid integrated circuit that can be made ultra-thin by stacking green sheets and storing the components inside the board, then fitting a flat ceramic lid into the sealing part of the board and sealing it with resin. Regarding equipment.
近年、電子機器が大規模、高性能化するとともに、一方
では、小型・軽量化及び高信頼度が要求さｈてきている
。特に携帯用電子機器においては、小型・軽量化ととも
に、薄型化の傾向が著しく、こｈらの機器に使される混
成集積回路装置にも、超薄型化及び高信頼度化の要求が
厳しくなりつつある。In recent years, electronic devices have become larger and more sophisticated, and at the same time, there has been a demand for smaller size, lighter weight, and higher reliability. Particularly in portable electronic devices, there is a remarkable trend toward smaller and lighter weight as well as thinner products, and the hybrid integrated circuit devices used in these devices are also required to be ultra-thin and highly reliable. It is becoming.
従来、セラミック積層配線基板にＩＣチップ、積層セラ
ミックチップコンデンサ等を搭載し、部品搭載部をセラ
ミック蓋にて樹脂封止した構造の混成集積回路装ｆｉｆ
ｉｔは、第１図に示すように、基板上に部品を搭載し、
凹形のセラミック蓋にて封止しているため、その高さは
、基板のＩｆさに、セラミック蓋の高さ、を合せたもの
になり、超薄形化は困難であった。更に、セラミック蓋
を基板に取付ける際位置合せが必要であるため杵築性が
悪く、又、基板上にセラミック蓋による凸部分が生じる
ため製造工程中のセラミック蓋部分の破損等による不良
発生が多くなるため、その製造歩留は低く、信頼性上に
も問題があった。Conventionally, a hybrid integrated circuit device fif has a structure in which IC chips, multilayer ceramic chip capacitors, etc. are mounted on a ceramic multilayer wiring board, and the component mounting area is sealed with resin using a ceramic lid.
As shown in Figure 1, it mounts components on a board,
Since it is sealed with a concave ceramic lid, its height is the sum of the If of the substrate and the height of the ceramic lid, making it difficult to make it extremely thin. Furthermore, since alignment is required when attaching the ceramic lid to the substrate, the mounting performance is poor, and since a convex portion is created by the ceramic lid on the substrate, there are many defects due to breakage of the ceramic lid portion during the manufacturing process. Therefore, the manufacturing yield was low and there were also problems in terms of reliability.
従って、本発明の目的は従来の混成集積回路装置の上記
の欠点をなくシ１．超薄型化が可能で、製造歩留が高く
、シかも高信頼性を有する混成集積回路装置を提供する
ことに、ある。SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to eliminate the above-mentioned drawbacks of conventional hybrid integrated circuit devices. An object of the present invention is to provide a hybrid integrated circuit device that can be made ultra-thin, has a high manufacturing yield, and has high reliability.
本発明の混成集積回路装置は、厚膜導体、厚膜抵抗等の
印刷されたアルミナグリーンシートと、部品搭載部や封
止用セラミック蓋の部分がくシ抜かねたアルミナグリー
ンシートとを積層し、一括焼成してセラミック積層配線
基板を形成し、次に部品搭載部にＩＣチップ、積層セラ
ミックチップコンデンサ等を搭載し、しかる後に平板状
のセラミック蓋を、基板の封止部分にはめ込み、樹脂封
止したことを特徴とする。The hybrid integrated circuit device of the present invention is obtained by laminating an alumina green sheet on which thick film conductors, thick film resistors, etc. are printed, and an alumina green sheet in which parts of the component mounting area and the sealing ceramic lid cannot be removed. A ceramic laminated wiring board is formed by batch firing, and then IC chips, laminated ceramic chip capacitors, etc. are mounted on the component mounting area, and then a flat ceramic lid is fitted into the sealing part of the board and resin sealed. It is characterized by what it did.
次に本発明による実施例を図面を参照して説明する。第
２図は、本発明による混成集積回路装置の断面図及びそ
の製造方法を示す図である。Next, embodiments according to the present invention will be described with reference to the drawings. FIG. 2 is a cross-sectional view of a hybrid integrated circuit device according to the present invention and a diagram showing a method of manufacturing the same.
スルホール７がそわぞｈ形成さねたアルミナグリーンシ
ート１から５に、対応１．たパターンの厚膜導体６をス
クリーン印刷法にて印刷し形成する（第２図Ａ）、ここ
で前記グリーンシート３及び４には、部品搭載用のくり
抜き８が開けられておシ、グリーンシート５には、制止
用セラミック蓋がはめ込み可能なくり抜き９が設けられ
ている。Corresponding to alumina green sheets 1 to 5 in which through holes 7 are formed into fissures 1. A thick film conductor 6 with a pattern is printed by a screen printing method (FIG. 2A). Here, the green sheets 3 and 4 are provided with hollows 8 for mounting components. 5 is provided with a cutout 9 into which a ceramic stopper lid can be fitted.
次に前記グリーンシート１から５を重ね合せて一括焼成
してセラミック積層配線基板を形成した（第２図Ｂ）後
、前記グリーンシート３及び４のくシ抜き部８で形成さ
ノまた積層セラミック配線基板の部品搭載部に、ＩＣチ
ップ１０及び１８Ｍセラミックテップコンデンサ１１を
搭載しく第２図Ｃ）、しかる後、平板状のセラミック蓋
１２を前記グリーンシート５のぐシ抜き部で形成さハた
、セラミ １ツク蓋取付部分にはめ込んで、搭載部品を
樹脂刺止し、混成集積回路装置を製造した（第２図Ｄ）
。Next, the green sheets 1 to 5 are stacked and fired at once to form a ceramic laminated wiring board (FIG. 2B). The IC chip 10 and the 18M ceramic TEP capacitor 11 are mounted on the component mounting portion of the wiring board (FIG. 2C), and then a flat ceramic lid 12 is formed using the cut-out portion of the green sheet 5. A hybrid integrated circuit device was manufactured by inserting a single piece of ceramic into the lid attachment part and attaching the mounted components with resin (Fig. 2D).
.
かかる方法で製造された混成集積回路装置は超薄型であ
り、製造歩留が高く、信頼性上も充分に満足のいくもの
であった。 １
これは本発明による混成集積回路装置が、セラミック配
線基板を使用して、搭載部品を基板内部に格納した構造
であるためと、セラミック蓋の位置合せが不要で、工数
が短く、又基板上にセラミック蓋の凸部分が生じないの
で、セラミック蓋の破損等による歩留の低下がなかった
ための効果と考えらｈる。The hybrid integrated circuit device manufactured by this method was ultra-thin, had a high manufacturing yield, and was fully satisfactory in terms of reliability. 1 This is because the hybrid integrated circuit device according to the present invention uses a ceramic wiring board and has a structure in which the mounted components are housed inside the board. Also, there is no need to align the ceramic lid, the number of steps is short, and This is thought to be due to the fact that no convex portions were formed on the ceramic lid, so there was no decrease in yield due to breakage of the ceramic lid.
第１図は従来の混成集積回路装置の構造を示す断面図で
あり、第２図は本発明の実施例の混成集積回路装置の構
造及び製造工程を示す断面図である。
なお図において、１，２，３，４．５・・・・・・アル
ミナグリーンシート、６・・・・・・厚膜導体、７・・
・・・・スルーホール、８，９・・・・・・＜シ抜き部
、１０・・・・・・ＩＣチップ、１１・・・・・・積層
セラミックチップコンデ５−
ンサ、１２・・・・・・セラミック蓋、である。
６−
ヌ （１）
睡FIG. 1 is a sectional view showing the structure of a conventional hybrid integrated circuit device, and FIG. 2 is a sectional view showing the structure and manufacturing process of a hybrid integrated circuit device according to an embodiment of the present invention. In the figure, 1, 2, 3, 4.5... alumina green sheet, 6... thick film conductor, 7...
...Through hole, 8, 9...<Cut out part, 10...IC chip, 11... Multilayer ceramic chip capacitor, 12... ...It's a ceramic lid. 6- nu (1) sleep
Claims (1)
ーンシートと、部品搭載部がくり抜かれた第２のアルミ
ナグリーンシートと、封止用セラミック蓋の部分がくり
抜かねた第３のアルミナグリーンシートとが積層さね、
一括焼成されて形成されたセラミック積層配線基板の、
前記部品搭載部にＩＣチップ、積層セラミックチップコ
ンデンサ等が搭載され、平板状のセラミック蓋が前記セ
ラミック積層配線基板の封止部分にはめ込まねて樹脂封
止さねていることを特徴とする混成集積口 。 路装置。[Claims] A first alumina green sheet on which a thick film conductor, a thick film resistor, etc. are printed, a second alumina green sheet in which a component mounting part is hollowed out, and a sealing ceramic lid part. The third alumina green sheet that could not be hollowed out is laminated,
Ceramic laminated wiring board formed by batch firing,
A hybrid integration characterized in that an IC chip, a multilayer ceramic chip capacitor, etc. are mounted on the component mounting portion, and a flat ceramic lid is fitted into a sealing portion of the ceramic multilayer wiring board and sealed with a resin. Mouth. road device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58119215A JPS6010647A (en) | 1983-06-29 | 1983-06-29 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58119215A JPS6010647A (en) | 1983-06-29 | 1983-06-29 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6010647A true JPS6010647A (en) | 1985-01-19 |
Family
ID=14755792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58119215A Pending JPS6010647A (en) | 1983-06-29 | 1983-06-29 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010647A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0204568A2 (en) * | 1985-06-05 | 1986-12-10 | Harry Arthur Hele Spence-Bate | Low power circuitry components |
| US4705917A (en) * | 1985-08-27 | 1987-11-10 | Hughes Aircraft Company | Microelectronic package |
| JPH05501658A (en) * | 1989-11-28 | 1993-04-02 | レオコーア インコーポレーテッド | small contour catheter |
-
1983
- 1983-06-29 JP JP58119215A patent/JPS6010647A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0204568A2 (en) * | 1985-06-05 | 1986-12-10 | Harry Arthur Hele Spence-Bate | Low power circuitry components |
| EP0204568A3 (en) * | 1985-06-05 | 1988-07-27 | Harry Arthur Hele Spence-Bate | Low power circuitry components |
| US4705917A (en) * | 1985-08-27 | 1987-11-10 | Hughes Aircraft Company | Microelectronic package |
| JPH05501658A (en) * | 1989-11-28 | 1993-04-02 | レオコーア インコーポレーテッド | small contour catheter |
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