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JPS5952073B2 - Diode matrix integrated thermal head - Google Patents

Diode matrix integrated thermal head

Info

Publication number
JPS5952073B2
JPS5952073B2 JP52001457A JP145777A JPS5952073B2 JP S5952073 B2 JPS5952073 B2 JP S5952073B2 JP 52001457 A JP52001457 A JP 52001457A JP 145777 A JP145777 A JP 145777A JP S5952073 B2 JPS5952073 B2 JP S5952073B2
Authority
JP
Japan
Prior art keywords
thin film
lead wire
group
thick film
glaze layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52001457A
Other languages
Japanese (ja)
Other versions
JPS5387238A (en
Inventor
尚三 武野
光彦 田代
嘉久雄 三原
雅一 岩上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marcon Electronics Co Ltd
Toshiba Corp
Original Assignee
Marcon Electronics Co Ltd
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marcon Electronics Co Ltd, Tokyo Shibaura Electric Co Ltd filed Critical Marcon Electronics Co Ltd
Priority to JP52001457A priority Critical patent/JPS5952073B2/en
Publication of JPS5387238A publication Critical patent/JPS5387238A/en
Publication of JPS5952073B2 publication Critical patent/JPS5952073B2/en
Expired legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/315Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
    • B41J2/32Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads

Landscapes

  • Electronic Switches (AREA)
  • Non-Adjustable Resistors (AREA)

Description

【発明の詳細な説明】 本発明は感熱ヘッドに感し、特にダイオードアレーが同
一基板上に一体に形成された感熱ヘッドに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thermal head, and more particularly to a thermal head in which a diode array is integrally formed on the same substrate.

フ 従来の感熱ヘッドは抵抗体として酸化ルテニウム等
を用いた厚膜ヘッドと窒化タンタル等を用いた薄膜ヘッ
ドに大別される。
F. Conventional thermal heads are broadly classified into thick film heads using ruthenium oxide or the like as a resistor and thin film heads using tantalum nitride or the like as a resistor.

前者は製造が容易で量産に適し比較的大型のヘッドがで
きるという利点がある。
The former has the advantage of being easy to manufacture, suitable for mass production, and capable of producing relatively large heads.

しかし、微細な・パターンが作りにくく高密度記録には
不適当であり、又応答が遅い等の欠点がある。後者はほ
ぼこの逆の長所および短所を有している。ところでこの
ような感熱ヘッドの構造としては、微小な発熱用抵抗体
素子を耐熱性絶縁基板上に一列に配列’し、印字すべき
文字単位にグループ化して選択的に通電するいわゆるド
ットプリンタ形式のものが広く用いられている。このよ
うな形式のヘッドでは、発熱抵抗素子を各グループに共
通の電極で駆動するため各抵抗素子に逆流防止用ダイオ
ードを含む選択駆動回路が接続される。
However, it is difficult to form fine patterns and is unsuitable for high-density recording, and has drawbacks such as slow response. The latter has almost opposite advantages and disadvantages. By the way, the structure of such a thermal head is a so-called dot printer type in which minute heating resistor elements are arranged in a line on a heat-resistant insulating substrate, grouped into characters to be printed, and selectively energized. are widely used. In this type of head, a selection drive circuit including a backflow prevention diode is connected to each resistance element in order to drive the heating resistance element with an electrode common to each group.

従来の感熱ヘッドでは発熱抵抗部と選択駆動回路は、そ
れぞれ別個に製造しこれらを一体化していたが、これら
を同一基板上に集積回路技術により形成したヘッドも提
案されている(例えば実用昭50−80442号公開公
報)。このような一体化構造のヘッドはダイオードアレ
ーを含む選択駆動回路部分のリード線を多層配線する必
要があるが、薄膜でこのような多層配線構造のヘッドを
製造する場合は次のような問題が生ずる。すなわち、多
層配線する場合には下層配線と上層配線の間に、例えば
SiO。膜のような絶縁層を介在させるが、絶縁層を蒸
着をあるいはスパッタリングにより形成するとピンホー
ルの存在が避けられず、このピンホールを介して上下の
配線が短絡する欠点がある。又、SiO2膜にエツチン
グ形成したスルーホールを介して上下のリード線を接続
する場合、段差により接触不良となり易い欠点もあつた
。このような故障の生じる確率は抵抗体素子の数が増大
し回路が大規模化するに従つて多くなり製造の歩留りを
低下することになる。本発明はこのような欠点を除去し
た薄膜ヘツドの提供を目的とするものである。
In conventional thermal heads, the heating resistor and selection drive circuit were manufactured separately and integrated, but heads in which these were formed on the same substrate using integrated circuit technology have also been proposed (for example, in the 1970s). - Publication No. 80442). Heads with such an integrated structure require multilayer wiring for the lead wires of the selection drive circuit including the diode array, but when manufacturing heads with such a multilayer wiring structure using thin films, the following problems arise. arise. That is, in the case of multilayer wiring, for example, SiO is placed between the lower layer wiring and the upper layer wiring. An insulating layer such as a film is interposed, but when the insulating layer is formed by vapor deposition or sputtering, the presence of pinholes is unavoidable, and there is a drawback that upper and lower wirings are short-circuited through these pinholes. Furthermore, when connecting the upper and lower lead wires through through holes etched in the SiO2 film, there is a drawback that poor contact is likely to occur due to the difference in level. The probability of such a failure occurring increases as the number of resistor elements increases and the scale of the circuit increases, resulting in a decrease in manufacturing yield. The object of the present invention is to provide a thin film head that eliminates these drawbacks.

すなわち本発明のヘツドは、耐熱性絶縁基板の表面に厚
膜リード線群を形成し、その上を厚膜グレーズ層で覆う
That is, in the head of the present invention, a group of thick film lead wires is formed on the surface of a heat-resistant insulating substrate, and the lead wire group is covered with a thick film glaze layer.

そしてこの厚膜グレーズ層の上面に発熱抵抗およびリー
ド線を薄膜により形成するようにしたものである。この
ような本発明によれば多層配線部分の下層リード線群は
厚膜により構成されるため、この上にグレーズ層を厚膜
で形成してもこの熱処理過程において酸化等により損傷
がなく、又グレーズ層も十分な膜厚とできるためピンホ
ール形成の怖れもない。すなわち、例えば前述の従来例
のようにすべての回路を薄膜で構成しようとするとグレ
ーズ層のピンホールによる短絡等が生じ、これを防止す
るためグレーズ層のみを厚膜で構成しようとする、厚膜
の製造過程において基板を900〜1000℃で焼成す
る際、先に形成された薄膜回路が酸化されたり剥離する
等の損傷が生じ実現不可能であつた。この点本発明では
下層リード線を厚膜で構成し、上層回路を薄膜で構成す
るいわゆる厚膜と薄膜回路の組み合せにより従来の問題
点を解決したものである。以下本発明を実施例により説
明する。
A heating resistor and lead wires are formed as thin films on the upper surface of this thick film glaze layer. According to the present invention, the lower lead wire group of the multilayer wiring part is made of a thick film, so even if a thick glaze layer is formed thereon, there will be no damage due to oxidation or the like during this heat treatment process. Since the glaze layer can also be made sufficiently thick, there is no fear of pinhole formation. In other words, if all the circuits are made of thin films as in the conventional example mentioned above, short circuits will occur due to pinholes in the glaze layer, and in order to prevent this, only the glaze layer is made of thick film. When baking the substrate at 900 to 1000[deg.] C. in the manufacturing process, damage such as oxidation and peeling of the previously formed thin film circuit occurred, making it impossible to realize. In this regard, the present invention solves the conventional problems by combining the so-called thick film and thin film circuits, in which the lower layer lead wire is made of a thick film and the upper layer circuit is made of a thin film. The present invention will be explained below with reference to Examples.

第1図乃至第3図は本発明の感熱ヘツドの構成を製造フ
冶セスに従つて示す上面図、第4図は第3図の一点鎖線
A−Nに沿つた断面図である。
1 to 3 are top views showing the structure of the heat-sensitive head of the present invention according to the manufacturing process, and FIG. 4 is a sectional view taken along the dashed line AN in FIG. 3.

先ず第1図に示すようにアルミナ基板11に下層リード
線群12を厚膜法により形成する。すなわちリード線の
材料としては、銀−パラジウム合金(Ag−Pd)ある
いほ金(Au)を用い、これらの粉末ペーストをスクリ
ーン印刷により所定パターンに塗布し、しかるのち90
0〜1000℃で焼成す・る。次に第2図に示すように
下層厚膜リード線群12の端子導出部13を残して基板
11の全面にグレーズ層14を厚膜法により形成する。
First, as shown in FIG. 1, a lower lead wire group 12 is formed on an alumina substrate 11 by a thick film method. That is, as the material for the lead wire, silver-palladium alloy (Ag-Pd) or gold (Au) is used, a powder paste of these is applied in a predetermined pattern by screen printing, and then 90%
Fire at 0-1000℃. Next, as shown in FIG. 2, a glaze layer 14 is formed on the entire surface of the substrate 11 by a thick film method, leaving the terminal lead-out portions 13 of the lower thick film lead wire group 12.

このグレーズ層14は、例えばSiO2を主成分とした
ガラスを用いる。このグレーズ層14の形成工程におい
ては、前記の下層リード線群12の所定部分にスルーホ
ール15を明ける。このスルーホール15は、スクリー
ン印刷の際のパターニングにより構成する。このように
厚膜法でグレーズ層14を基板11のほぼ全面に形成し
た後、第3図に示すように発熱用の抵抗素子配列16、
上層リード線群]7、共通電極18を薄膜法により形成
する。
This glaze layer 14 is made of, for example, glass containing SiO2 as a main component. In the step of forming the glaze layer 14, through holes 15 are formed in predetermined portions of the lower lead wire group 12. This through hole 15 is formed by patterning during screen printing. After forming the glaze layer 14 on almost the entire surface of the substrate 11 using the thick film method, as shown in FIG.
Upper layer lead wire group] 7. The common electrode 18 is formed by a thin film method.

すなわち、先ずグレーズ層14の表面に耐エツチング性
の5酸化タンタル(Ta2O5)を塗布し(図示せず)
、その上に例えばチツ化タンタル(Ta−N)抵抗膜を
高周波スパ゛人タリングにより付着し、続いてリード層
として例えばクロム金(Cr−Au)膜をスパツタリン
グあるいは真空蒸着により付着する。そしてこのように
付着されたTa−N膜およびCr−Au膜の不要部分を
エツチングにより除去し、所定の形状、ピツチ、個数の
上層リード線群17、共通電極18を形成する。その後
、前記のように構成されたリード線群17の一部をホト
エツチングにより除去してTa−N膜を露出させ抵抗素
子配列16とする。この抵抗素子配列]6の表面部分に
は第4図に示すようにTa2O5のような耐摩耗性の保
護膜19を設ける。ダイオードアレーが形成された半導
体チツプ20を共通電極18と上層リード線群17間に
設置しフリツプチツプにより接続する。そしてこの半導
体チツプ20を含む電極部一帯に耐湿耐熱性のシーリン
グ材21を塗布硬化して完成する。なお下層リード線群
12と上層リード線群17との接続は前記スルーホール
15を介してCr−Au膜のスパツタリングすることに
よつて行なわれ特別な工程は不要である。
That is, first, etching-resistant tantalum pentoxide (Ta2O5) is applied to the surface of the glaze layer 14 (not shown).
For example, a tantalum titanide (Ta--N) resistive film is deposited thereon by high-frequency sputtering, and then, as a lead layer, for example, a chromium-gold (Cr--Au) film is deposited by sputtering or vacuum evaporation. Then, unnecessary portions of the Ta--N film and Cr--Au film thus deposited are removed by etching to form the upper layer lead wire group 17 and the common electrode 18 in a predetermined shape, pitch, and number. Thereafter, a portion of the lead wire group 17 configured as described above is removed by photoetching to expose the Ta--N film and form the resistor element array 16. As shown in FIG. 4, a wear-resistant protective film 19 such as Ta2O5 is provided on the surface of the resistive element array 6. As shown in FIG. A semiconductor chip 20 on which a diode array is formed is placed between the common electrode 18 and the upper layer lead wire group 17 and connected by a flip chip. Then, a moisture-resistant and heat-resistant sealing material 21 is applied and cured over the entire area of the electrode section including the semiconductor chip 20, thereby completing the process. Note that the connection between the lower layer lead wire group 12 and the upper layer lead wire group 17 is performed by sputtering a Cr--Au film through the through hole 15, and no special process is required.

第5図は第3図に示す感熱へツドの等価回路図である。FIG. 5 is an equivalent circuit diagram of the heat-sensitive head shown in FIG. 3.

図の番号は第3図と対応するように付されている。上記
した本発明によれば次のような効果が得られる。
The figures are numbered to correspond to those in FIG. According to the present invention described above, the following effects can be obtained.

(1)下層リード線群を耐熱性の厚膜で形成するため多
層配線用の絶縁層として厚膜法によるグレーズ層を用い
ることがで゛きるためピンホールが無く短絡や接続不良
等の製造不良が少ない。
(1) Since the lower lead wire group is formed from a heat-resistant thick film, it is possible to use a glaze layer using the thick film method as an insulating layer for multilayer wiring, so there are no pinholes and manufacturing defects such as short circuits and poor connections. Less is.

(2)多層配線の下層にリード線の一部を上層に抵抗素
子を含む薄膜回路を形成する構造としたため基板表面の
凹凸をな<すためのグレーズ層を、多層配線用の絶縁層
と兼用でき構造が簡単で製造も容易である。(3)上記
のような多層配線構造の結果、比較的複雑な製造工程を
要する薄膜回路の製造工程が後になるため、多層配線工
程の製造不良によつて全体のへツドを不良とすることが
避けられ歩留りが向上する。
(2) Because the structure is such that a part of the lead wire is formed in the lower layer of the multilayer wiring, and a thin film circuit including a resistive element is formed in the upper layer, the glaze layer used to create unevenness on the board surface is also used as an insulating layer for the multilayer wiring. It has a simple structure and is easy to manufacture. (3) As a result of the above-mentioned multilayer wiring structure, the thin film circuit manufacturing process, which requires a relatively complicated manufacturing process, is carried out later, so manufacturing defects in the multilayer wiring process do not cause the entire head to be defective. This can be avoided and yields can be improved.

(4)下層リード線群およびグレーズ層を厚膜法により
製造するため、多層配線のためのスルーホールの形成は
スクリーン印刷時のパターニングででき、薄膜法の場合
のようなエツチング工程は不用である。
(4) Since the lower lead wire group and glaze layer are manufactured using the thick film method, through-holes for multilayer wiring can be formed by patterning during screen printing, and the etching process unlike the thin film method is unnecessary. .

又厚膜法ではスクリーン印刷で設けたスルーホールは焼
成工程によりガラスが適当に流れエツジが滑らかとなる
ため、上層リード線群の付着が完全であり接続不良が生
じない。エツチングにより形成したスルーホールではこ
の点が問題となる。(5)上層リード層は薄膜法で付着
するため、スルー−ホールを介する下層リード層との接
続は特別な工程を要することなく行なうことができ製造
工程が著しく簡略化される。
In addition, in the thick film method, the glass flows through the through holes formed by screen printing and the edges are smoothed by the firing process, so that the upper layer lead wire group is completely attached and no connection failure occurs. This is a problem with through holes formed by etching. (5) Since the upper lead layer is attached by a thin film method, connection with the lower lead layer via through-holes can be made without requiring any special steps, and the manufacturing process is significantly simplified.

なお本発明は、上記の実施例に限定されるものでないこ
とは言うまでもない。
It goes without saying that the present invention is not limited to the above embodiments.

例えば基板、リード線、抵抗、グレーズ層の材料は上記
実施例以外のものも利用できる。
For example, materials other than those in the above embodiments may be used for the substrate, lead wires, resistor, and glaze layer.

又、第5図の等価回路図に示されるような配線はスルー
ホールの数を減少するため特殊な配線としたが、例えば
第6図に示すような回路としてもよい。
Further, although the wiring shown in the equivalent circuit diagram of FIG. 5 is a special wiring in order to reduce the number of through holes, a circuit as shown in FIG. 6 may be used, for example.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第3図は、本発明の感熱ヘツドの構成を製造
工程順に示す上面図、第4図はこのへツドの第3図A−
A’に沿う断面図、第5図はこの感熱へツドの等価回路
図、第6図は本発明の他の実施例を示す感熱へツドの等
価回路図である。 11・・・・・・耐熱性絶縁基板、12・・・・・・
(下層)厚膜リード線群、14・・・・・・グレーズ層
15・・・・・・スルーホール、16・・・・・・抵抗
素子配列、17・・・・・・ (上層)薄膜リード線群
、18・・・・・・共通電極、20・・・・・・ダイオ
ードアレー半導体チツプ。
1 to 3 are top views showing the structure of the thermal head of the present invention in the order of manufacturing steps, and FIG.
5 is an equivalent circuit diagram of this heat-sensitive head, and FIG. 6 is an equivalent circuit diagram of a heat-sensitive head showing another embodiment of the present invention. 11...Heat-resistant insulating substrate, 12...
(Lower layer) Thick film lead wire group, 14... Glaze layer 15... Through hole, 16... Resistance element array, 17... (Upper layer) Thin film Lead wire group, 18... Common electrode, 20... Diode array semiconductor chip.

Claims (1)

【特許請求の範囲】[Claims] 1 耐熱性絶縁基板上に配線された厚膜リード線群と、
このリード線群を含む前記基板面を覆うように形成され
た厚膜グレーズ層と、このグレーズ層上に配列された薄
膜抵抗素子群と、これらの薄膜抵抗素子群に対応して設
けられたダイオード素子群とを備え、前記薄膜抵抗素子
群の隣り合う所定数を単位グループとし、前記厚膜リー
ド線を前記所定数と等しい数だけ設けると同時に、隣り
合う前記単位グループにおいて、対称の位置にある薄膜
抵抗素子の間の前記薄膜リード線の経路形状を略U字と
し、この略U字の経路形状を有する薄膜リード線及び前
記厚膜リード線群とを前記グレーズ層に形成されたスル
ーホールを介して相互に接続する手段とを有することを
特徴とするダイオードマトリクス一体化感熱ヘッド。
1 A group of thick film lead wires wired on a heat-resistant insulating substrate,
A thick film glaze layer formed to cover the substrate surface including the lead wire group, a thin film resistance element group arranged on this glaze layer, and a diode provided corresponding to the thin film resistance element group. an element group, a predetermined number of adjacent thin film resistive element groups are defined as a unit group, and the thick film lead wires are provided in a number equal to the predetermined number, and are located at symmetrical positions in the adjacent unit groups. The path shape of the thin film lead wire between the thin film resistance elements is approximately U-shaped, and the thin film lead wire having the approximately U-shaped path shape and the thick film lead wire group are connected to the through hole formed in the glaze layer. 1. A diode matrix integrated thermal head, characterized in that it has a means for interconnecting the diode matrix through the diode matrix.
JP52001457A 1977-01-12 1977-01-12 Diode matrix integrated thermal head Expired JPS5952073B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52001457A JPS5952073B2 (en) 1977-01-12 1977-01-12 Diode matrix integrated thermal head

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52001457A JPS5952073B2 (en) 1977-01-12 1977-01-12 Diode matrix integrated thermal head

Publications (2)

Publication Number Publication Date
JPS5387238A JPS5387238A (en) 1978-08-01
JPS5952073B2 true JPS5952073B2 (en) 1984-12-18

Family

ID=11501972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52001457A Expired JPS5952073B2 (en) 1977-01-12 1977-01-12 Diode matrix integrated thermal head

Country Status (1)

Country Link
JP (1) JPS5952073B2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5565576A (en) * 1978-11-09 1980-05-17 Fujitsu Ltd Thermal head
US4463359A (en) 1979-04-02 1984-07-31 Canon Kabushiki Kaisha Droplet generating method and apparatus thereof
JPS5743886A (en) * 1980-08-29 1982-03-12 Fujitsu Ltd Manufactue of thermal head
JPS5824464A (en) * 1981-08-04 1983-02-14 Rohm Co Ltd Manufacture of thermal printer head
JPS5859863A (en) * 1981-10-07 1983-04-09 Oki Electric Ind Co Ltd Thermal head
JPS5867474A (en) * 1981-10-19 1983-04-22 Toshiba Corp Thermal head
JPS58205780A (en) * 1982-05-26 1983-11-30 Toshiba Corp Heat sensitive printing head
JPS60199673A (en) * 1984-03-26 1985-10-09 Fujitsu Ltd Thermal recording head
JPS6143050U (en) * 1985-07-17 1986-03-20 株式会社日立製作所 thermal head

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JPS5387238A (en) 1978-08-01

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