JPS5946687A - Liquid crystal drive voltage generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Technical field of invention] Ru.

[Technical disadvantages of the invention]

The conventional 71 (crystalline motion circuit thread plate) for dynamic +Ij4 movement using the T and D bias method is shown.

That is, llf:': For example, small+r<17 in the circuit.
．． ．． 12 is a bias supply circuit which generates a bias voltage and supplies it to the upper Fj12''i'L voltage dividing circuit 11; I3 is a voltage dividing circuit 2t2 which is connected to the above 'f!f voltage dividing circuit; Segment drive T11; IE V +
, Vs of each segment signal input, select according to the ethical level to select segments l-f of the liquid crystal q/indicator;
'j'llll Ml' Shiko 11 (Supply 1111 Lung 111
This is the segment 1 pivot circuit, and the segment 4 of the liquid crystal display is
The common electrode ↑r1 of the front power distribution dividing circuit 11 is supplied to each common electrode terminal.

In the above-mentioned voltage dividing circuit 11VC, the same 41V
(1st to Pn4 1st generation antis with antisense value R 14. to 144
is connected in series 1, and its -Q:i+i FJ,? fA,
yl[vI)I) K1 concubine f1. The other end C is connected to the bias input terminal Z5 via an IJ channel type MOS-FET (insulated gate type electric current transistor) Ql. And upper ff11. ': P channel type MOS F' E T Q in 11 rows to the resistor 141 of rr
2 is l-f, 1154's 11℃ 19144 is parallel to N channel type 40 S -F E T
Q s is If 4::, and these two F
Freno signal W is input to each gate of E'r'Q2 + Qs to 11n.

-Also, 1''!jl Ft
) 711: Pressure v, and 11'l i! l: 3rd fL'v, 49 "stirrup" of resistor 143 and fourth resistor 144
)] point (node +v,), pressure V3 and (・,11,
:lI! I, i[-segment 1ill, jii,
1) It is supplied as segment IR dynamic pressure to 7, "t.fr, :l?, I 6 is the standby inverter that inputs S T B Y, 171□2 This inverter 16σ) Output and display enable signal E N A RL CP is derived from a two-man power AND circuit, and this AND circuit jl! , 317 are derived from the gate (D) of the F E TQ+.

On the other hand, 1 ++, +, + (1) P channel type blO
8-FETQ4 and 31 hard N channel type #, 40S
-F E T Q 5 T Q 6+Q7 and 1
1'A column connection NΔ1 and the resistance 14□ of the 4 rods
- Parallel to the series circuit of J44 'I)''11'11
'c's 71. ing. And Ll″lself F E
'I' Q 5 The valley gates of Park and Q are both one mountain j',
l, 'j li ni sa IL, F E 1゛041)-
and (47・h gate, Jl, : ) on mountain 1me 3,
“j; has been done. Sara Vko, Mae i!l-: F E
'r Q2, Q3 gate and F T? ,'
L'tlii.

An inverter 18 is connected between the gate of C7 and I3<v.

Size/ko, Z 9 (r-J: CIJ OS Sinch C
Yes, this) 1゜jtJ: N-channel type hl OS
F Ii: After i' Q 6 and IAOS -F E'l'' Q of the P-boon irregular form are parallel, ・A
, as well as F E 'I'' Q, gate 7F
At the output of El'Qo's gate, the inverter ■ is connected to the gate of El'Qo.

tl to m-7;A' of this Clvf OS switch 19
First 1 to 14; end λ2 resistor 142 and third resistor 14.
The j~k・ノ1'1 point (two-do J2) & tej is connected, and the other end is the front tif F fj '1. '(J, 5
:J※l,,l, of J*l, :Kiyō and Q, :When I'□rll is made to the point, the common output ρ to the river is H to 1 to +5 child 20. = Earth, the above Cb40 S switch 19 inverter output p; 11 is the previous t:L: F F T Q a
+ Gate K(2) of Q 6 1. and FET
Output of the gate Q moss 2 manual NAND circuit 21 of Q,'
1M is r-poor <-1: This Nando times 1 Raku 21
The duty fFr No. d 1 is floated as one of the human power, and the blank fif No. B L I' is floated as the other human power.
J K is written as z, l',,j. 1 ), + li: T Q , ~Q , , CI
4 OS switch 19, switch 1, '7i 21 and common output I11 (child 20 I;] 1, + s for the number di, i.e. '-151~
1) C7, L te 4 lit for 34 duet d, -d4 (Near S 11>゛<i VCIrJ-f
i+'+abbreviation! t) 1 #, ll, (1)
), -il,, 2 illusion et al.7.

Dimension/(-1 before 1, 11...-Ding Asu A: i' at times 1 Raku 12, illusion 1, fu line '1!, Ir'Vl) I)
421: (anti [(,, R2FC, 1: fi min HE
lytebias r11. The pressure VLOD is generated.

Next, the 21st:''1 will be explained using jnn 11:, <1 tJ) operation VC as f, >, lij%. Frame transmission W irJ, "0", "■" level passes to father n>:, l, □1, this Freno No. 111 W's 0" Lebel Ukomako and "1" level) 1-1, respectively.
d, (I11, dl only I:゛, I shown) is I
ff” (rX occurs. Ito, -r hemorrhoids 1+, l<!I
II) jl function motor 1'
bNAnt, cp becomes 1”, F E T Q is turned on, and this F E 'r Q and the fourth (7)
tj (, anti-144 and) ring member; point (/-t N 4
) ノ+i.

o:, V 4 is in the bias of bias input 911.1 child 15 I[-(V r,, L; o LC:)! 7. ``Mountain'', r+! i-view'・ft IIE Vn+
+ and J2jjl',", Node N 4 mountain: Moon: v,
The output between (1n, the difference; 'i', 1~"HG+
4 of 11 (Anti 141 to 14. For 1 use! Sign. So (-, zu, and 1 (C between 11)), blank Shingetsu it L, N K is "1" !321 to Ql, inversion i $ '? j rl 1 of 1 is output. is “O” l/bell between μJ1, FETQ3 section j: off, FET
Q2i1', J: turns on, and the voltage of node N, V,i
l, VDD, node I ('iff of 2, +E v 2
is (VDI] - VLc[) ) x 〒1'VLql) and [j? of node N3. 1 King V*);I, (Vl)I)
-VLa+]) x -; -1-VL C1). At this time, the output n111 of the inverter 8 turns FTG TQ+It off and FETQ on.

Therefore, when the duty signal +'rd1 is +11'', the output of the NAND circuit 21 is "Q", the CIJOS switch 19 is off, the output of the inverter J is 1", and Ii'l'i
', TQs! Q6 is a main VC, common output)"111! ("20, F""' Q6 +
ILJ: (1',
]i! ir, E, V4. = VLcD Ka4 Warel. After doing this, the irises d1 is “0”
The 11th sword [to the river (is, the output of Nando times 1?7j 21 is 1", the CM OS switch I9 is on, the output of the inverter is "0", Ii' E T Q !+ and Q6 are off, kj, c to common output 1'+Iti child 20
vos switch 19 to jf+Ute/-1x
+q ,, o Current] 7rt, I:E V 2
= (Vl) Ll -Vl, OD)
r, Of) Ka QHj will be.

Next, the frame I1G) W is "1F Dr T Q s is on, FET Q2 is off, no 1' N s F!i: Ir:, V s in the period of "■ Lebel.
ItJ: VLOI-), +'i]' of node N2
, IT: V2 is (VDD - Vl, (+D)
x〒-1=VL CL:l, I pressure V at node N is (
VDIJ - VLOD )X' + v+, c II
becomes. Also, at this time, the output lIO' of the inverter 18
FE'TQ4 is turned on and Fl sword TQ7 is turned off by l. Therefore, te 0 needi (14 gin d 1)
1''+1111t-Ll;Ll The output of NAND circuit 2I is N01, CM OF3 switch 19p; :A
-7, Ear Hark 1) Output force "1", F F, i
'Q! I'1. L: ozQn is on (・su,
Common output 1'; iA child 20 j (-(1,, jFE
T Q, 4', Q! , %"1 mountain Jite FR, ylp, Fit'I', r3 VI) n
−7,+;, Q, j 07+.

7, for this t, Dudy (number ()1 is “0”
When opening and opening of ``l', 1, the output of NAND circuit 2I is t'', C
I, 4 o s switch I9 is on, input 7 terminal 1
(A) 'fl force is "0", FETQp and Qn or cutoff)? 1, common output/terminal 2o K i, J: c
u OS switch 19.)1] to node N2
li ■ bad day' [mountain, + ": v2= (\'DI) -
vr=co) X-+VT, CI) is J, l,, I,
I'l-Z). 1. '7c, top-down! (] Out 1 (+3Lru< -11″) V
C sea 1, liquid, 11~-multi7Jt+1-1 2:÷σ), 1yjH4 selected segment?
Displayed by Riko on the I way - [Sn power is applied.

” Kneebo Shida fψ show old 1-11 (for 1 work, J1
= During the appearance 11J1 (vomit blank ear 0e Ei-'r
Tii-'* is "0" and left note, NAND circuit 2] output (, tWllll, C1, J OS switch 1
9 is turned on, and a signal W is sent to the common output terminal 20 between nodes 1(2) and 7(,
H: IF, V2: (VDD - VLCD) X
, +VLOD ly: ``t'a ware, 7 L
The current voltage V of the node N2 is applied to the current voltage V of the node N2, = (VDD-vLaD)X T +
VLOD appears, and the liquid crystal display does not reach the operating type IE of the liquid crystal even if 6 segments are selected, so the display d
, not done.

Note that from the bias supply circuit 12 to the bias supply circuit V1
, CtD to city 1. By applying it to the E dividing circuit 11, the front-2 voltage dividing circuit 11 and the segment fllR1
11υ circuit 13, etc. of an integrated circuit? 1'i, 7
Atsushi Pressure and Shi”: KAI Shitsuta; rl + work ty IH’s Ytl
In order to kick the j-crystal display, it is necessary to move '+! :, it is now possible to browse IE. This 1. j,%
In this case, in order to reduce the fluctuation of the bias voltage VLCD, i
=, J: , f1^ of the resistors R, , R2 of the bias supply circuit 12 are connected directly to the voltage divider circuit 11 by three resistors (first to third resistors 14, to 143 or second ~
It is essential to set it sufficiently smaller than the resistance value 3R of 41 (resistance 14□ to 144) of 21λ4.

1/This, Q12, display command No. 13 ENABLCP reaches 109 in the display drive prohibited mode, FET Q
+ goes off, 11X: anti-14. ~14. i+;
t: +g, 1llit does not flow, previous::1: /-
Do N, , N? , , l'J3. r, r,,
Name '+'5. ICE kJ', 'r4f, rl
? , 'ji,;, l'h VDD K thickness fi L
, <? c Ol";' = 4i'1 time'd?+ is erased within 1'J/+'ti, the force is low;/LA,,
Similarly, when in standby mode in tJ: b14 = 1jth mode, S T l'l Y is 11.
'', the output of the inverter 16 becomes ``10'' VCfx, so the F port ``I'' Q + '', ``I'' turns off,
Resistors 141-14. He plays the role of VC for Nigu J and Tunjiif, so that there is no flow delta.

[Back: Problems with the sewing technique]

However, I agree with the bias! /6I2 years old? 1.
11(anti-1'(,,II(2t/ζ) always flows in r
As mentioned above, R,, R2<, q R
There is a relationship such that [(,, R2 & ζ large 'bo flow is i'
rir, so 'rj'j 11th 1 LCD!
Ill, As for the entire dynamic circuit system, Q, 1:, The above two cases are shown J,! Is it in lA immobile IL mode or during standby? It cannot be said that the f'i cost and accommodation capacity are necessarily sufficiently reduced.

[Purpose of the invention]

The present invention was made in consideration of the small INK of the above-mentioned company, and has a display IQ of 1" and a liquid crystal 11J which can significantly reduce the power consumption when bias supply is not required, such as in the prohibited city mode.
J11'i, which provides a sho generation circuit.

[・Invention 4+1+1. That is, the liquid crystal "K Ii+IIit generation circuit" of the present invention arranges a switching element in a column 11 to the voltage dividing resistor for bias + ii rlT generation of the bias supply circuit, and when the bias voltage is not supplied, the above switching element is Off condition, Su・
11 is a special imitation.

Therefore, in the crystal driving prohibited [1-mode, etc., the bias (If < power consumption of the detection circuit?] is eliminated, so the power consumption of the circuit of the present invention 11) is significantly reduced compared to the conventional circuit. .

[Embodiment of the invention] Hereinafter, one embodiment 1 of the present invention will be described with reference to FIG. 1i:11.
will be explained in detail. 3. V (not shown in M) (see Figure 1)
(Compared to the liquid crystal active circuit system of
Connect one end of the resistor R1 of the bias supply circuit 32 to one end of the 1st arm + M pin (bottle) (~, (it, !,
q In the liith C1~, between the external bin 31 and the 6th place VSS of the suchi city, there is a N Bouyannel type t, AO8-FgT.
Q+o 4〉! : #IiL, this FF, T
The output of the OR circuit 17 is also connected to the gate of Q+o.
The starting point is kon so that C is continuous, and the rest t: 1. Since it is the same, it is shown in Figure 3. The same parts as in Figure 1 are given the same symbols and their explanations and explanations are '+'i. Do W6.

Elegant i, 11″If according to the precepts, display (Rini Docho 11
During standby in Himode and Ansui 1
- mode, as mentioned above, when the output of the AND circuit 17 becomes 0'l, both F E ('J' Q and QIO are turned off, so as mentioned above,
Not only does the current stop flowing to the f-1 to fourth 11 (resistance 14.-74.), but also the bias generation coarse portion of the bias supply circuit 32 [1ff, the flow is f) I
The power consumption at this time will be reduced compared to the conventional example. Ministry 1@.

Note that this investigation is not limited to the above-mentioned royalty fee; Good, also front 4 [2F z TQI
In place of O, Rime connects a switch element in series with the bias generation voltage dividing resistor of the bias supply circuit 12, and uses this switch element to cut off the voltage applied to the bias generation resistor when no bias is required. Although a liquid crystal drive voltage generation circuit is shown, the present invention is of course not limited to this, and can of course be applied to liquid crystal drive voltage generation circuits using other bias methods.

[Efficacy of invention, center]

As mentioned above, the liquid crystal i'(KrriI+ voltage generation circuit) of the present invention can significantly reduce the power consumption during bias voltage supply failure such as t-C1 display, IJ(KIIJ prefecture [L mode, etc.) !1 cost electricity!1”f
It is possible to realize a display drive system that takes full advantage of the characteristics of the C modified liquid crystal display.

4.1 also:, 4 fii 12i1 simple; explanation No. 11”
', I is the conventional LCD chant! 1. Configuration 1 showing a circuit system 1. Figure 1 and Figure 2 show p, +' (operation in Figure 1 ~, 'l'jI', l'I waveform Ill, shown for clarity)13 The figure is a configuration explanatory diagram showing an embodiment of the liquid crystal drive Bltj+mount pressure generation circuit according to the present investigation.

11...71j Pressure component force 11 times h+7. 15...Bias input terminal, 32...Bias supply circuit% Ql
+Q+o...FgT0

Claims (1)

[Scope of Claims] A liquid crystal display device includes a voltage divider circuit for generating an IC voltage, a bias supply circuit for supplying a bias voltage to the voltage divider circuit, and a bias voltage divider circuit for generating an IC voltage; It is inserted between the bias output terminal of the supply circuit and the bias input (944) of the 117. voltage divider circuit.1 switch element and the bias generator /'f1 voltage divider resistor of the bias supply circuit. The second switch element pushed into the straightening 11 is 11in t, , -1: fA~1
bias the switch element and the second switch element'
Ii (Liquid crystal characterized by being controlled to be turned off when Ifl supply fails!1■ Dynamic voltage generation [[11th path.