JPH0756515Y2 - 2-phase signal generation circuit - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is a single phase in a GaAs MESFET digital IC circuit → 2
The present invention relates to improvement of a phase signal generation circuit.

<Prior art> As a method of realizing a single-phase → two-phase signal generation circuit with a GaAs MESFET IC, a circuit using a differential pair as shown in Fig. 2.

A circuit that uses the difference in delay time between the logic gates as shown in FIG.

There is known a circuit or the like for obtaining a non-inverted output by inputting a signal to the source side of a BFL (Buffered FET Logic) as shown in FIG.

<Problems to be Solved by the Invention> However, when the above circuits (1) to (2) are used as BFL, the circuit shown in FIG. 2 requires a separate power supply, and there is a problem that the logic level goes wrong. The circuit shown in the figure has a problem in that the number of elements increases and the output becomes unstable due to process changes. In the circuit shown in FIG. 4, the source input side has low impedance, so it cannot be driven by an ordinary logic gate. There was a problem.

The present invention was made in view of the above-mentioned problems of the conventional technology.
The purpose is to realize a single-phase → two-phase signal generation circuit that can operate stably in the FL circuit.

<Means for Solving the Problem> The configuration of the present invention for solving the above problem is a first FET including a first FET whose source terminal for outputting an inverted signal in response to an input is connected to a common potential. A two-phase signal generation circuit comprising a BFL circuit and a second BFL circuit including a second FET whose gate terminal that outputs a non-inverted signal corresponding to the input is connected to a common potential. The first and third FETs are connected to the gate terminal of the
Is connected to the output from the source follower of
The output from the second source follower in which the sources and drains of the fifth and sixth FETs are connected is input to the source terminal of T, and the gate width of the sixth FET is adjusted to match the switching timing and voltage level. Is characterized by making the gate width of the second FET about twice.

<Operation> Since the source follower circuit is provided before the inverting / non-inverting circuit, the input impedance on the source input side rises and the IC circuit can operate as a BFL circuit.

<Embodiment> The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 1 is a well-known buffer circuit composed of 4 FETs and a diode, and 2 is a drain terminal of the 3rd FET 2a of the 2 FETs is connected to V _DD (+ 4V), and its source side is a diode 2
The first source follower circuit is connected to the drain terminal of the fourth FET 2b via c and has the source terminal and the gate terminal connected to Vss (−3V).

Reference numeral 3 is a second source follower circuit, in which the drain terminal of the fifth FET 3a of the two FETs is connected to V _DD (+ 4V), and the source side thereof is connected to the drain terminal of the sixth FET 3b. FET3b source and gate terminals are Vss
It is connected to (-3V). The output from the buffer circuit 1 is connected to the gate terminal of the third FET 2a of the first source follower circuit and the gate terminal of the fifth FET 3a of the second source follower circuit.

Reference numeral 5 is a well-known first BFL circuit including the first FET 5a, and the output terminal from the first source follower circuit 2 is connected to the gate terminal of the first FET.

Reference numeral 6 is a known second BFL circuit including the second FET 6a, and the output terminal from the second source follower circuit is connected to the source terminal of the second FET 6a. The gate width of the sixth FET 3b of the second source follower circuit is about twice that of the second FET 6a of the second BFL circuit. Ten
Is an input terminal, 11 is an output terminal of the first BFL circuit, and 12 is a second BFL circuit.
This is the output terminal of the FL circuit.

In the above configuration, if a high level signal is input to the input terminal 10, the signal is inverted and branched by the buffer circuit 1, and one of the branched signals is passed through the first source follower circuit 2 to the first BFL. It is input to the circuit 5 and inverted again to output a high level signal from the output terminal 11. Also, the other branched signal is input to the second BFL circuit 6 via the second source follower circuit 3, but here the output from the source follower circuit 3 is input to the source terminal of the second FET. Therefore, its source potential rises. As a result, the gate voltage seen from the source side drops, and the output terminal of the second BFL circuit becomes low level. In this case, the second FE
A current flows through the sixth FET 3b through the source of T, but this current flow affects the timing of the signal that becomes the output of the second BFL (the time and voltage level of the high level and the low level differ from each other). This deviation is adjusted by the gate width of the sixth FET, but in the experiment, it could be realized by doubling the sixth gate width from the gate width of the second FET 6a.

<Effect of Device> As described above in detail with the embodiments, according to the present invention, the source terminal of the second FET of the second BFL circuit 6 is connected to the source and drain of the fifth and sixth FETs. The input from the second source follower connected to
Since the gate width of the FET 3b is about twice as large as the gate width of the second FET 6a, the input impedance becomes high like a normal logic gate and it can be used as an IC internal logic element.
Therefore, when compared to the conventional example of FIG.
Since it is a level, there is no need to use a separate power supply, and when compared with the conventional example of FIG. 3, it is possible to operate at high speed because it is composed only of the inverter system logic that operates at the highest speed among the logic gates. Yes, it is stable against process changes.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a two-phase signal generating circuit of the present invention, and FIGS. 2 to 4 are diagrams showing a conventional example. 1 ... Buffer circuit, 2 ... First source follower circuit, 2a ...
3rd FET, 2b ... 4th FET, 2c ... Diode, 3 ... 2nd source follower circuit, 3a ... 5th FET, 3b ... 6th FET, 5 ... 1st BFL circuit, 5a ... 1st FET, 6 ... 2nd BFL circuit, 6a ... 2nd FET.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location H03K 19/00 101 B (72) Inventor Tsuyoshi Yagihara 2-932 Nakamachi, Musashino City, Tokyo Horizontal Within Kawa Denki Co., Ltd. (72) Inventor Akira Uchida 2-932 Nakamachi, Musashino City, Tokyo Yokogawa Denki Inc. Within (72) Hiromi Kamada 2-932 Nakamachi, Musashino City, Tokyo Yokogawa Denki Incorporated (72) Inventor Sadaharu Oka 2-932 Nakamachi, Musashino-shi, Tokyo Yokogawa Electric Co., Ltd. (56) Reference JP-A-53-139456 (JP, A) JP-A-62-195915 ( JP, A) JP-A-1-147916 (JP, A)

Claims (1)

[Scope of utility model registration request] 1. A first BFL including a first FET whose source terminal, which outputs an inverted signal in response to an input, is connected to a common potential.
A second circuit including a circuit and a second FET whose gate terminal that outputs a non-inverted signal corresponding to the input is connected to a common potential
A two-phase signal generation circuit composed of a BFL circuit, wherein the output from a first source follower in which a third and a fourth FET are connected via a diode is connected to the gate terminal of the first FET. , The source terminal of the second FET is the fifth and sixth FETs
The gate width of the sixth FET is about twice as wide as the gate width of the second FET in order to input the output from the second source follower in which the source and the drain of are connected and to match the switching timing and the voltage level. A two-phase signal generation circuit characterized in that