JPS58202621A - Digital/analog converting circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a weighted constant current type D/A conversion circuit, and more particularly, to a D/A conversion circuit suitable for mounting as an MO8 integrated circuit on the hip.

As an example of a weighted constant current type D/A conversion circuit implemented in an MO8 integrated circuit, there is a (b) path as shown in FIG. 1, for example. This circuit uses digital human power Z1 r Zz +...
...zn is supplied to the gate terminal of n switches 5FIIIT (insulated gate field effect transistor) 8118+1...an, and this switch 8FET81, sl... day Constant current M 8FETs Q, +,' connected directly to n, respectively.
Q18. ...consists of Qn. The above constant current M engineering SFF? lTQ,,.

The same bias voltage 8 is applied to the gate terminals of Q, R...Qn. Switch V 5FFlt by digital human power z1゜z2...zn
T.S.

S! ......When 8n is turned on, each constant current M 81" ICT Q, 1 * Ql + ""
'・Qn has 1, 21,...2, respectively.
” A constant 111 m of i is made to flow n.

The sum of these currents flows through the resistor RIC, thereby creating an analog voltage V across both terminals of the resistor R in response to the digital input. ut is generated and D/A conversion is performed.

However, in the above D/A conversion circuit, MIS
When the channel width W and channel length of pHIT are L and T, the ratio of current flowing through the IC is determined by the W/L ratio of M8F1nT. . Therefore, if the channel length Li is constant, the current ratio is determined by the ratio of the W dimensions, and if the minimum W dimension of L8B (lower bit) is determined, the MO8 dimension increases by 2 times, 4 Double, eight times...
and grows exponentially. As a result, as the number of input bits increases, the area occupied by the circuit increases.

Also, if the channel vergence w'l is constant, W, flow is:
M engineer 8PK! TQ1-Q, determined by the L dimension of n, L r
＞L! >--> L n. Therefore,
MO8 dimensions can be made smaller. However, in this case, since the M-type 8FEtT with a large current has a small L dimension, there is a problem that the p'Wtm shielding is reduced due to variations in the L dimension.

Therefore, this invention divides the weighted constant current M-type 5FET into several groups in bit order, and each constant-current M-type SFI
[Pi to give a bias voltage to iT” Ill, I
An ass circuit is provided for each of the above groups, and a constant current M1 day Fll! is grouped with each bias circuit. By creating a current mirror circuit configuration in which the current can be increased depending on the ratio of T and MO8 dimensions, it is not necessary to make the MO8 dimensions exponentially large in order to obtain the required current ratio. This reduces the area occupied by the entire circuit, and also reduces the
The overall purpose is to prevent a decrease in current accuracy due to variations in the channel length of T.

The present invention will be explained below based on the drawings.

FIG. 2 shows an embodiment of the present invention.

- As an example, a circuit for 4-bit digital input iD/A conversion will be explained.

Switch opening 11'FIi! The gate terminal of TSt~day 4 has a weight t of 2°, 2', 2" + 2".
The awaited digital input Z, -z4 is supplied.

When the digital inputs z1 to z4 are respectively set to fL"1// level, the corresponding switch opens 5FKTS.

~S 4 *E off state't4 nisat'L, 1'f
When cZL-Z4 is brought to the ol level, it is put into the 'fang) state.

Upper Hr2 switch M engineering sFm'rst ~84 K is,
Corresponding to each bit of the digital input, a switch s, ~
Weighted constant current circuits 5FKTQ, .about.Q4 are connected in series to flow currents of i, 21, and 41.81 to s and n, respectively.

This constant current M engineering 5FFiTQ, t ~ Q, 4 is Q + l
It is divided into two groups, +Q,2 and Q3*Q4, and bias circuits 1a and 1b are provided corresponding to these groups, respectively. All in all,
A bias voltage V from the bias circuit W11 a is applied to the gate terminal of the constant current M S F Fi T Q I and Q2.
A bias voltage VBb from a bias circuit mtb is applied to the gate terminals of the M circuit aPITQ3 and Ql.

The bias circuits 1a and lb are composed of load resistors R4 and Rb whose one end is connected to the power supply voltage v0°, and the resistors R,
, Rb are connected in series to n721., Rb, respectively. Constant current M engineering 8F
It consists of FiTQIL and Q, b.

For the resistors Ra and Rb, a diffusion layer formed on a semiconductor substrate or a discrete component externally attached to the IC is used. And resistance R1! L and J) are not limited to the height, but are set so that the magnitude of the resistance is Ra=2Rb, for example.

This causes the flow to the M-type 13FETQ, a, Q, b.
The electric current work, which is the same as the electric current work, is made so that the current work is 2 work.

Further, the above-mentioned M-type SFl]TQa and Ql) have their respective n gates and sources connected to operate in a saturation region. And M Engineering 8F] IfTQ, a and Qb
The channel width W and length L are W,=W1), La==
It is formed to become Lb.

M engineer 8 of the bias circuit 1a above 'I! E T Q,
eL is the weight constant current M of the first group
IIT Qi *Q8 and current mirror circuit connection n
ing. In addition, M engineering 8FllllTQ of bias circuit 1b
b is the weighted constant current M of the second group 811'1ll
TQ3 and Ql are connected in a current mirror circuit.

Figure 3 shows this bias circuit and weighted constant current M 8PBT.
Extract and show the current mirror circuit connection with.

In this current mirror circuit, M5FF)TQ
, a and Ql both operate in the saturation region, then M and E?
F B T Q, electric current work flowing to a, and M work 8F
The stream flowing into ETQt is solved by the following formula.

Engineering, = βa/2 (vaa vtha)” -...
(1) 1N=β+/2 (v()I vthl)”
...(2) Here, vGa and vGL are M
Engineering 8F1 [ITQ,! With the gate voltage of L and Q, 1, this is equal to ■Ba. t7t.

β1. βa, vtha, and Vth+ are f'LM I
S IFITQ, a+Qt conductance t1'' narrowing constant and threshold direct voltage.Vtha and 7th
+ indicates IFIIIT formed on the same conductor board at the same time.
Then the direction will be the same.

Furthermore, β is M engineering 8F] I! T's career transition #IjJf
tμ, the dielectric constant and total thickness of the gate insulating film are #OX, respectively.

Ru.

Therefore, from equations (1) and (2), 11/work, = β1/
β1=L, La Toe 9, in the current mirror circuit, constant current M 8
IF] The ratio of the current flowing through 1riT is W of M-8FET.
/L ratio.

Therefore, the constant current f biased by the bias circuit 1a
LM engineering 8FFiTQ, becomes the current tItix flowing through *.

Here, M engineering 8Fl'l'Q, a, Ql + L' of Qa
By keeping i constant and forming the M process 5FITQ, a, Q+, Qvt so that "a" wt + W, "2Wl", 12=21 can be obtained.

Similarly, bias episode lol! The following also holds true between 11b and the weighted constant current M unit S'PITQs, Ql of the second group. Therefore, Ll)=L,=L, and w,=
2 W b, W4: M engineering J so that it becomes 2 VIH
By forming 3F]nTQb*Qs, Q, 4, it is possible to obtain 14=211=4.

Moreover, as mentioned above, the bias cycle W6ta.

1b is engineering 1. ．． = 1 cmg so that 2 engineering a, so for constant current M engineering 11 F IT Q,, -0,4, n, zo t'LL+ + 211-411-811
A current of n will now flow.

In this way, according to the circuit of this embodiment, the constant current M
Fl! TQs and Q, channel width W of 4, MI8F
I! There is no need to increase TQ by 4 or 8 times.
Just double and quadruple times.

Therefore, in this real 11/jJ example, the upper bit MO8
The dimensions can be made much smaller than conventional ones, and the M plane PI4 of the entire circuit can be reduced.

Also, the upper bit M-engine 8FF! Also the channel length of T?
Since there is no need to make it very small, it is possible to prevent the current #'/4 degrees from decreasing due to variations in the L dimension.

Ao, Ra=J, %La'=”Lb, 'b=1/2
Even if it is set to Wa, the same effect as in the above embodiment can be obtained.

Furthermore, the bias circuit can be constructed as shown in FIG. 4 by using a complementary M5yBT.

In this embodiment, instead of the resistors Ra, R1), the load M
工8FITQ(1,Q(1 is used and
The above M-engine 8FETQ0. V-engine which gives bias to Qd by current mirror circuit connection 8F ET Q, ,
A resistor R1 is provided.

Therefore, the constant current M of the bias circuit 8? BTQa and Q,
Flowed to b 21.4 [RI l and M engineering 8F K
T Q, 6 and load MIIFII! 'I'Q,,Q,
(Determined by the W/L ratio of 1. Also, relatively internal M
The number of resistors RZO consisting of a diffusion layer with a large surface depth can be reduced.

In addition, in the pre-loading example, the 4-bit digital input iD
Although the path (2) in which /A changes has been described, the present invention can also be applied to a circuit that converts digital input 'iD/A with a larger number of bits.

In that case, weighted constant current M SF]riTQ, , ~Q
It is also possible to divide the circuit into many groups and provide a general bias circuit for applying bias to each group by connecting a current mirror circuit.

As explained above, the D/A conversion circuit according to the present invention includes:
Weight constant current M 5F11tT'i Divide into multiple groups, separate the bias circuit gold film corresponding to each group, and constant current VISFIII which configures the entire bias circuit.
Since it is connected to the weighted constant current V 8 FIIIT and a current mirror circuit, the necessary current ratio can be obtained lcM08
It is necessary to increase the size exponentially as the entire size advances toward the upper bits, and the area occupied by the entire circuit is reduced. Also, the channel length of the weighted constant current V type fiPET'
Since it is not necessary to make ft too small, there is an effect that a decrease in the current of 111 degrees due to variations in channel length can be prevented. lll','
.

[Brief explanation of the drawing]

” Fig. 1 is a circuit diagram showing a conventional weighted constant current type D/A conversion circuit, and Fig. 2 is an implementation example of a D/A conversion circuit according to the present invention.
Figure 3 is a circuit diagram showing the connection between the bias circuit and the constant current M5FET in a Karen circuit, and Figure 4 is a circuit diagram showing all other embodiments of the bias circuit. . 1! Ll lb...bias circuit h sl ~8n
...Switch construction 8FBlT%Q,l~Qn...Weighted constant current M construction 5FIIIT0 Agent Patent attorney Usui 1) L4 up to Figure 3 and Figure 4 L4 -129=

Claims (1)

[Claims] A D/A conversion circuit including n switches to which n bits of digital input are supplied, and constant current transistors with different weights connected in series to each of the switches, The transistors are divided into a plurality of groups, a bias circuit is provided corresponding to each group, and a constant current transistor constituting each bias circuit is connected to the weighted constant current transistor in a current mirror circuit. A D/A conversion circuit with all the following features.