JPS594032A - Pressure welding type semiconductor device - Google Patents
Pressure welding type semiconductor deviceInfo
- Publication number
- JPS594032A JPS594032A JP11294482A JP11294482A JPS594032A JP S594032 A JPS594032 A JP S594032A JP 11294482 A JP11294482 A JP 11294482A JP 11294482 A JP11294482 A JP 11294482A JP S594032 A JPS594032 A JP S594032A
- Authority
- JP
- Japan
- Prior art keywords
- plate
- pressure
- semiconductor element
- contact
- base body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔−発明の技術分野〕 この発明は、圧接型半導体装置ζ二関する。[Detailed description of the invention] [-Technical field of invention] The present invention relates to a pressure contact type semiconductor device ζ2.
電力用半導体装置の発展に伴ない圧接型半導体装置が多
くなった。これは、半導体基体内で生じる電力損失によ
る発熱を抑制するため、加圧接触型にして半導体素子の
2つの面から熱をはこび出すことを主眼とするものであ
る。With the development of power semiconductor devices, the number of press-contact type semiconductor devices has increased. The main purpose of this is to use a pressurized contact type to radiate heat from two surfaces of the semiconductor element in order to suppress heat generation due to power loss occurring within the semiconductor substrate.
圧接型半導体装置は実用に際しては、第1図に示すよう
に多くの構成物よりなる半導体スタックを組むのが一般
的である。第1図において半導体素子基体10の一方の
面を例えばモリブデン等からなる温度補償板11に接触
せしめ、他方の面をタングステン等からなる機械的支持
′板I2に接触させる。これら二つの板11.12の外
側に電極金属スタンプ7 、? 、 14を介してそれ
ぞれA/等からなる冷却フィン15.16を設ける。2
2は外囲器である。更に一方の冷却フィン15は、絶縁
板17および鋼等からなる点接触治具19を介して加圧
板2θと接触させ、他吐
方の冷却フィン16は、然縁板18を介して加圧板21
に接触せしめる。下側の加圧板2ノは通常加圧時には固
定板となり、上部の加圧板20側から矢印の方向に力を
加えることにより、半導体素子基体10は、電気的、熱
的に外部と接続される。この構造は半導体スタックと呼
ばれる。When a pressure contact type semiconductor device is put into practical use, it is common to assemble a semiconductor stack consisting of many components as shown in FIG. In FIG. 1, one surface of a semiconductor element substrate 10 is brought into contact with a temperature compensation plate 11 made of, for example, molybdenum, and the other surface is brought into contact with a mechanical support plate I2 made of tungsten or the like. Electrode metal stamps 7 on the outside of these two plates 11.12, ? , 14 are provided with cooling fins 15, 16 each consisting of A/etc. 2
2 is an envelope. Further, one cooling fin 15 is brought into contact with the pressure plate 2θ via an insulating plate 17 and a point contact jig 19 made of steel or the like, and the other cooling fin 16 is brought into contact with the pressure plate 2θ via a natural edge plate 18.
contact with. The lower pressure plate 2 normally serves as a fixed plate during pressurization, and by applying force in the direction of the arrow from the upper pressure plate 20 side, the semiconductor element substrate 10 is electrically and thermally connected to the outside. . This structure is called a semiconductor stack.
@1図の点接触治具I9の目的を第2図を用いて説明す
る。半導体素子基体30を金属スタンプ31、絶縁物3
2、点接触治具33及び加圧板34からなる加圧スタッ
ドを考えた時、加圧板34の底面、即ち点接触治具3.
?側力;同図の如く軸(c−c’)に対して直角の面で
かυ1場合にも、半導体素子基体30にかたよった圧力
が加わらぬように一点で力を伝達しようとするのが点接
触治具3,9の目的である。The purpose of the point contact jig I9 shown in Figure 1 will be explained using Figure 2. A semiconductor element substrate 30 is attached to a metal stamp 31 and an insulator 3.
2. When considering a pressure stud consisting of a point contact jig 33 and a pressure plate 34, the bottom surface of the pressure plate 34, that is, the point contact jig 3.
? Side force: Even in the case of υ1 in a plane perpendicular to the axis (c-c') as shown in the figure, the force is transmitted at one point so that uneven pressure is not applied to the semiconductor element substrate 30. This is the purpose of the point contact jigs 3 and 9.
ところで第1図の如く構成されたスタックにおいて、半
導体素子基体10の面内応力分。布を実測すると第3図
の如くなる。実線Aが温度補償板11と接する側の半導
体素子基体10の表面近傍の応力分布であり、実線Bは
冷却フィン15と絶縁板17の境界面における応力分布
である。横軸りのR8は温度補償板11の半径である。By the way, in the stack configured as shown in FIG. 1, the in-plane stress of the semiconductor element substrate 10. When we actually measured the cloth, it looked like the one shown in Figure 3. A solid line A is the stress distribution near the surface of the semiconductor element substrate 10 on the side in contact with the temperature compensating plate 11, and a solid line B is the stress distribution at the interface between the cooling fins 15 and the insulating plate 17. R8 along the horizontal axis is the radius of the temperature compensation plate 11.
図の如<:A、B共中心部(X:0 )の応力が極めて
高い。これは、第1図で示した点接触治具I9が外から
一点で力を受は伝達するため力が中央に集中するためで
ある。この上う(二応力が集中すると、部分的に熱抵抗
がトったり、電力集中を起こしたり゛し、最終的には半
導体素子基体が破壊する問題点をもっていた。As shown in the figure, the stress at the center (X:0) of both A and B is extremely high. This is because the point contact jig I9 shown in FIG. 1 receives and transmits force from the outside at one point, so the force is concentrated at the center. Moreover, when two stresses are concentrated, the thermal resistance may be partially exceeded or power may be concentrated, which ultimately leads to the destruction of the semiconductor element substrate.
本発明は上記の点に鑑み、半導体基体内の応力分布を均
一にして信頼性向」二を図った圧接型半導体装置を提供
するものである。In view of the above-mentioned points, the present invention provides a press-contact type semiconductor device in which the stress distribution within the semiconductor substrate is made uniform and the reliability is improved.
本発明は、第1図のような半導体スタックにおいて点接
触治具と半導体素子基体との間に、周辺部が中央よりも
肉厚であって、加圧時の変形により半導体素子基体の面
内応力分布を均一にする圧力分散用部材を介在させる。The present invention provides a semiconductor stack such as the one shown in FIG. 1 in which the peripheral portion is thicker than the center between the point contact jig and the semiconductor element substrate, and deformation occurs when pressure is applied to the semiconductor element substrate. A pressure dispersion member is interposed to make the stress distribution uniform.
本発明によれば、半導体基体の内部応力を均一化して、
部分的なコンタクトによる電力集中や熱抵抗の増大によ
る破壊を防雨し、圧接型半導体装置の信頼性向tが図ら
れる。According to the present invention, the internal stress of the semiconductor substrate is made uniform, and
It is possible to prevent damage caused by power concentration and increased thermal resistance due to partial contact, and to improve the reliability of the press-contact type semiconductor device.
本発明の一実施例を図を用いながら説明する。 An embodiment of the present invention will be described with reference to the drawings.
第4図は本発明の一実施例(二おける圧力分散用部材と
しての金属板41であって、同図(a))i断面図、同
図(h)は平面図である。図の如く、金属板41は中心
部の厚さより周辺部の厚さ力を厚し)ものでA/または
Cu等力)らな&】、例えトf直1蚤D=601を程度
の場合、周辺部と中111部の厚みの差が30〜40(
μm)程度でよXI)。このようにつくられた厚さの不
均一な金属板41を第5図に示す如く、絶縁板17と冷
却フィン15の間に挿入して図の上部から矢印の向き1
′″−加圧する。なお第5図において、@1図と対し6
する部分には第1図と同一、符号を付しである。力をよ
、・点接触治具17を通過するどきに軸(C−C’)の
中央に集中するが金属板41のところで周端部が厚いこ
とによって力の伝達力を中央部よI)密となる。その結
果点接触治具19のところで集中した力が再び分散され
て均一化するため、半導体素子基体IOには面内C二1
ヨヲ新一様な力カー力ロわることになる。FIG. 4 is a cross-sectional view of one embodiment of the present invention (a metal plate 41 as a pressure dispersion member in FIG. 2 (a)), and FIG. 4 (h) is a plan view. As shown in the figure, the metal plate 41 is thicker at the periphery than at the center. , the difference in thickness between the peripheral part and the middle part is 30 to 40 (
(μm) XI) As shown in FIG. 5, the metal plate 41 having a non-uniform thickness made in this way is inserted between the insulating plate 17 and the cooling fins 15, and is moved in the direction of the arrow 1 from the top of the figure.
''' - Pressure is applied. In addition, in Figure 5, 6
The same parts as in FIG. 1 are given the same reference numerals. When the force passes through the point contact jig 17, it is concentrated at the center of the axis (C-C'), but due to the thick peripheral edge of the metal plate 41, the force is transferred to the center I) It becomes secret. As a result, the force concentrated at the point contact jig 19 is again dispersed and made uniform, so that the in-plane C21
A new and uniform force will be lost.
@6図は本実施例による温度補イ賞板11と半導体素子
基体IOとの境界面における圧縮応力を測定したもので
ある。同図の如く、はぼ一様な応力分布が得られた。Figure @6 shows the measurement of the compressive stress at the interface between the temperature compensation plate 11 and the semiconductor element substrate IO according to this embodiment. As shown in the figure, a fairly uniform stress distribution was obtained.
尚、本発明のスタックを構成する場合、圧力分散用部材
を挿入する位置は、絶縁板と冷却フィンどの間にこだわ
らず、点接触治具と半導体素子基体の間ならどこでもよ
い。When constructing the stack of the present invention, the pressure dispersion member may be inserted anywhere between the point contact jig and the semiconductor element substrate, without being limited to between the insulating plate and the cooling fin.
第7図fa)、 (b)は本発明の他の実施例の圧力分
散用部材の断面図と平面図で、内径の異なる金属リング
を三枚重ねて構成1.ている。図の如く、中央部に金属
がないものも本発明に含まれる。FIGS. 7fa) and 7(b) are a sectional view and a plan view of a pressure dispersion member according to another embodiment of the present invention, which is constructed by stacking three metal rings with different inner diameters.1. ing. As shown in the figure, the present invention also includes a structure in which there is no metal in the center.
第8図(al 、 (b+は更に別の実施例の圧力分散
用部材の断面図と平面図で、同図fnlの断面で示す如
く両面が凹状になって、いてもよい。FIGS. 8A and 8B are a sectional view and a plan view of a pressure dispersion member according to another embodiment, and both sides may be concave as shown in the cross section of FIG.
第1図は従来の半導体スタックの断面図、第2図はその
点接触治具の働きを説明するための図、第3図は従来の
半導体スタックにおける半導体素子基体の面内応力分布
を示す図、第4図(al l (b)は本発明の一実施
例に用いる圧力分散用渣材としての金属板を示す図、第
5図は同実施例の半導体スタック構成図、第6図は同実
施例による半導体素子基体内の面内応力分布を示す図、
第7図(al 、 (blおよび第8図(a) 、 (
blは本発明の他の実施例の圧力分散用部材を示す図で
ある。
10・・・半導体素子基体、11・・・温度補償板、1
2・・・支持板、1.9 、 Z 4・・・金属スタン
プ、15゜16・・・冷却フィン、17.IFt・・・
絶縁板、19・・・点接触治具、20.21・・・加!
王板、22・・・外囲器、4)・・・金属板(圧力分散
用部材)。
出願入代押入 弁理士 鈴 圧式 彦第1図
第8図
154−
(a)
(b)Figure 1 is a cross-sectional view of a conventional semiconductor stack, Figure 2 is a diagram for explaining the function of the point contact jig, and Figure 3 is a diagram showing the in-plane stress distribution of a semiconductor element substrate in a conventional semiconductor stack. , FIG. 4(b) is a diagram showing a metal plate as a pressure dispersion residue material used in one embodiment of the present invention, FIG. 5 is a configuration diagram of a semiconductor stack of the same embodiment, and FIG. 6 is a diagram showing the same. A diagram showing in-plane stress distribution within a semiconductor element substrate according to an example,
Figure 7 (al, (bl) and Figure 8 (a), (
bl is a diagram showing a pressure dispersion member according to another embodiment of the present invention. 10... Semiconductor element substrate, 11... Temperature compensation plate, 1
2... Support plate, 1.9, Z 4... Metal stamp, 15°16... Cooling fin, 17. IFt...
Insulating plate, 19...point contact jig, 20.21...addition!
King plate, 22... Envelope, 4)... Metal plate (pressure dispersion member). Substitution for application Patent attorney Rin Ushiki Hiko Figure 1 Figure 8 154- (a) (b)
Claims (1)
ィンを積ね、これらの積層体に更に点接触治具を介して
加圧板を積ねて構成される圧接型半導体装置において、
前記点接触治具と半導体素子基体との間に、周辺部が中
央部より肉厚で加圧時の変形により半導体素子への面内
応力分布を均一にする圧力分散用部材を介在させたこと
を特徴とする圧接型半導体装置。In a pressure contact type semiconductor device, which is constructed by laminating metal stamps and cooling fins on both sides of a semiconductor element substrate, and further laminating a pressure plate on these laminated bodies via a point contact jig,
A pressure dispersion member is interposed between the point contact jig and the semiconductor element substrate, the peripheral part of which is thicker than the central part, and which deforms when pressurized to uniformize the in-plane stress distribution to the semiconductor element. A press-contact type semiconductor device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11294482A JPS594032A (en) | 1982-06-30 | 1982-06-30 | Pressure welding type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11294482A JPS594032A (en) | 1982-06-30 | 1982-06-30 | Pressure welding type semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS594032A true JPS594032A (en) | 1984-01-10 |
Family
ID=14599411
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11294482A Pending JPS594032A (en) | 1982-06-30 | 1982-06-30 | Pressure welding type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS594032A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0393997A (en) * | 1989-09-04 | 1991-04-18 | Showa Doboku Kk | Mud pressurizing propulsion device |
EP0441572A2 (en) * | 1990-02-07 | 1991-08-14 | Ngk Insulators, Ltd. | Power semiconductor device with heat dissipating property |
US5229915A (en) * | 1990-02-07 | 1993-07-20 | Ngk Insulators, Ltd. | Power semiconductor device with heat dissipating property |
-
1982
- 1982-06-30 JP JP11294482A patent/JPS594032A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0393997A (en) * | 1989-09-04 | 1991-04-18 | Showa Doboku Kk | Mud pressurizing propulsion device |
EP0441572A2 (en) * | 1990-02-07 | 1991-08-14 | Ngk Insulators, Ltd. | Power semiconductor device with heat dissipating property |
US5229915A (en) * | 1990-02-07 | 1993-07-20 | Ngk Insulators, Ltd. | Power semiconductor device with heat dissipating property |
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