JPS59184946A - Digital differential analyzer - Google Patents

Abstract

PURPOSE:To give an interruption to a host computer and to attain the processing at a high speed for a digital differential analyzer (DDA), by deciding the conditions from the arithmetic result of the DDA obtained with a command of the host computer and the combinations of interruption control bits added into the microcodes. CONSTITUTION:A host computer transfers the data needed for a DDA operation to actuate a DDA operation part. The DDA operation part reads out successively the shown microcodes OC which prescribe the operation and executes a DDA operation to obtain an increment component. An ''IRP'' bit is set into the code OC, and it is judged with this ''IRP'' bit and the result of the DDA operation whether the interruption decision processing is carried out or not. When the interruption conditions are satisfied, this information is given to a host CPU. At the same time, the operator where the interruption conditions are satisfied is stored. This improves the response performance and reduces the load of the host computer.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a digital differential analyzer (hereinafter abbreviated as DDA), and in particular, to a digital differential analyzer (hereinafter abbreviated as DDA), which is connected to a host computer and used as a gateway.
The present invention relates to a DDA in which the DA itself determines an interrupt condition and sends an interrupt signal to a host computer.

[Background of the invention]

FIG. 1 shows a general configuration in which DDAI is connected to a host computer 2. DDAI includes a host board 3 that controls connection with the host computer 1, a control unit 4 that controls the entire system, and a DDA operation The main component is a DDA calculation unit 5 that performs the following.

In the configuration shown in FIG. 1, normally, the DDAI is responsible for system dynamics analysis, and the host computer 2 is responsible for music control processing functions, thereby constructing a desired real-time control system.

In this case, the DDA calculation results are, for example, the temperature and flow rate of the process to be simulated (controlled).

It corresponds to a physical quantity such as pressure, and therefore it is necessary to feed back the corresponding control process in real time based on the value.

Conventionally, this determination process was performed on the host computer side. The reason for this is that the determination process must be performed on the overall value, but the DDA operation cannot process incremental data.

As a result, conventionally, the determination process as shown in FIG. 2 has been performed on the host computer 2 side.

That is, after the DDA initiation of calculation data transfer, T) DA activation, waiting for the DDA calculation end interrupt from DDAl, importing the calculation result, and performing condition judgment, and then checking if the condition is satisfied. If the condition does not hold, it checks whether the condition judgment for all cases has been completed, and if it is not completed, it further imports the operation results, and when it is completed, it starts a new I) D A. put on.

In this way, conventionally, the host computer has to import r)DN calculation results and perform judgment processing every time a DDA calculation is completed, which makes the processing complicated and reduces responsiveness/processing performance. This resulted in four hurdles when incorporating DDA as part of real-time control.

[Purpose of the invention]

The purpose of the present invention is to realize on the DDA side the condition judgment processing based on the results of DDA calculations, which was performed on the host computer side, and to easily display the judgment results in a post-calculation manner, so that the total of 1↑Tsuki IU is reduced. The object of the present invention is to provide a digital differential analyzer that improves the quantification of the response t'tE/S++14:jl and eliminates the burden of quantification.

[Summary of the invention]

In the present invention, in order to perform the 1-point processing that was performed on the host computer') 7;, 4:, and 16 side on the I) D A side, the result is transferred to 1) l). The infinitesimal J￥′ of a certain output variable
, minute ΔZ and the interrupt side sub-bit added in the microprogram are used to perform the false incident judgment process, and the result of 'l'l possible location ζ ri is recognized by the host computer by the interrupt signal. This is what I did.

[Embodiments of the invention]

Fig. 3 shows the processing flow in the host when four types of interrupt processing are performed according to the present invention: n: 4; When the interrupt condition is met, the actual iteration of 1 routine is executed.
A processing step in which the host computer takes in the straight line results from DI)8 and makes a condition determination is omitted.

FIG. 4 shows the implementation of the present invention (January 19), and mainly shows the DDA calculation section 5 of FIG. D
The DA calculation section 5 includes a control section 6 that controls DDA RUN and /5TOP, a timing circuit 7 that generates an operation timing signal, a microcode storage memory 8, and a DDA calculation operation.
Next, an arithmetic memory 9 and DDA for recording secondary incremental data.
The error detector 11 detects an overflow error and stops DI A, the DZ memory 13 stores DZ (output increment) data that is the result of DDA calculation, and the characteristic parts of the present invention.

Interrupt control circuit 12 and arithmetic unit No. for which the interrupt condition is satisfied
The main constituent element is the register 14 that stores .

FIG. 5 shows an example of the DDA microcode format used in the present invention. The key point here is that the "IR, P" bit is provided.

The 41st side bit is a bit that controls whether or not to perform interrupt determination processing using the calculation result of the DDA calculation unit. In FIG. 4, the microcode is stored in the memory 8, and the microcode is read out from the memory 8 and given as a human input signal 14 to the interrupt control circuit 12. Further, the interrupt control circuit 12 is given the DZ data 15 which is the calculation result of the DDA calculation unit 11, and as shown in a specific example in FIG.
is stored in the memory. FIG. 6 is a circuit diagram of a specific embodiment of the interrupt control circuit 12.

When the interrupt condition is met, the host CPU
In order to report this and at the same time to memorize which arithmetic unit the voice-over condition was established, the arithmetic unit NO field (EL, No I) in the microcode shown in Figure 5 is stored in the register 14.
Store everything.

FIG. 7 shows an operation time chart of FIG. 4.

Furthermore, regarding the relationship between r) Z memory and the establishment of interrupt conditions, see D.
D Output increments of decision elements (masks/windows/comparators) that are well known in the repertoire of DA operators.

It will be easier to understand if the DZ generation algorithm is defined. For example, the comparator's y register j/(
You can set the threshold for the condition to be met at any time n+f6: By setting it in advance, you can set the threshold for the first time in the register. When the input increment value (Σdyi) is equal to or greater than υJ1, the DZ data is generated as "1". However, the above decision element has been repeatedly used in the DDA calculation model, Whether or not to create the function r, Φ is determined by logical AND with the "I R, P" bits.

〔Effect of the invention〕

According to the present invention, since the fl'' determination process is performed on the DI) A side and the determination result is made known to the host computer by an interrupt signal, it is expected that responsiveness and processing performance of the host computer will be improved.

[Brief explanation of drawings]

Fig. 1 is a diagram showing a general system configuration in which a host computer and DDA are combined, Fig. 2 is a flowchart of judgment/161ri explaining the conventional technology, and Fig. 3 is an implementation of the judgment process according to the present invention. Example Flow Chart, FIG. 4 is a block diagram showing an embodiment of the DDA calculation section of the DDA according to the present invention, and FIG. 5 shows an example of the microcode format used in the present invention! +J,! , the 6th i/1 is the 4th
-Implementation 3/1l of the '-JIJ included system 0111 circuit shown in the figure
lt4i road map, Figure 7 is a tie for explaining Figure 4 α assistant action,
・, Dehab −1・. 5...t3 D A calculation section, 8... Microcode storage section Fig. 2

Claims (1)

[Claims] 1. The host computer is connected to D
A digital differential analysis system that receives data related to DA operations, sequentially reads out microcodes that define DDA operations using DDA activation commands, executes DDA operations, and sends a completion report to the host computer when execution is complete. In the machine, an interrupt control bit is added to the microcode that defines the operation of the DDA operation, and a condition is determined based on a combination of the interrupt control bit and the minute increment of the output variable that is the result of the DDA operation, A digital differential analyzer characterized by being provided with an interrupt control means for outputting an interrupt signal to a host computer when a condition is met.