JPH07120167B2 - Processing method and processing device for sequence control - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a sequence control processing method and processing apparatus, and more particularly to speeding up the processing.

[Conventional technology]

A conventional sequence control device (referred to as a sequence controller) is disclosed in Japanese Patent Application No. 59-36040. This conventional device has a bit register for exchanging data with the process input / output device, an arithmetic unit, and an accumulator for storing the arithmetic result. The data is read from the input / output device to the bit register, the logical operation is performed by the arithmetic unit, and finally the arithmetic result is stored in the accumulator.

FIG. 10 shows an example of AND processing in the sequence processing. Here, I1 is a read command (LD command),
I2 is an AND instruction, I3 is a write instruction (ST), and the addresses of the process input / output devices targeted by these instructions are indicated by PIO1 to PIO3, respectively. This sequence process can be written as:

(PIO3) = (PIO1). (PIO2) However, (a) shows the data (logical value) stored in the address a. This sequence processing is performed by the conventional sequence controller according to the flow shown in FIG. That is, each of instructions, read instructions (step 1101,1104,1107), the data transfer from the instruction address (process input and output device) or accumulator ACC of the read out instruction bit to the register (D _r) (step 1102, 1105, 1108) and the execution of the process instructed by the instruction (steps 1103, 1106, 1109).

FIG. 12 shows an example of OR processing in the sequence processing. Here, I4 is a read command, I5 is an OR command, and I6 is a write command. This sequence process is
It can be written as

(PIO6) = (PIO4) + (PIO5) This process is performed by the conventional sequence controller according to the flow shown in FIG. 13 (a). That is, also in this case, each of the instructions I4 to I6 has been executed by the processing of three steps.

[Problems to be solved by the invention]

In the above-mentioned conventional technique, at the time of executing the AND processing and the OR processing,
Since the process I / O device always reads data and performs logical operation, there is a limit to the speeding up of processing.

It is an object of the present invention to provide a sequence control processing method and processing device capable of speeding up sequence processing.

[Means for solving problems]

The above-mentioned purpose is 0, 1, or the second read from the process input / output device depending on the value (0 or 1) of the first data read from the process input / output device to the bit register and the type of instruction. It is achieved by providing a means for outputting any of the data as a calculation result, and for temporarily saving the previously obtained processing result when performing the calculation processing with a plurality of processing results as data. This is accomplished by providing stacking means.

[Action]

In the case of AND operation, when one data is 0, the answer is 0 regardless of the other data value, and when one data is 1, the other data value itself is the answer. In the case of OR operation, when one data is 1, the answer is 1 regardless of the other data value, and when one data is 0, the other data value itself is the answer. Therefore, whether 0 or 1 is set in the bit register as an answer from the judgment whether the instruction is an AND operation or an OR operation and the value of the first data read from the process input / output device (this is the first data itself. , It does not have to actually do anything because it has been set before the determination), or it is sufficient to read the second data from the process I / O device and set the value in the bit register, which is the same as the conventional accumulator. The data transfer and logical operation step, the step of reading the second data from the process input / output device even when the second data is unnecessary, and the like can be omitted, and the processing speed is increased. In addition, when performing the arithmetic processing of the previous processing result and the current processing result, the previous processing result is saved in a stack, and the saved value and the bit register value which is the current processing result The value of the bit register is judged and the value in the bit register is rewritten only when necessary to give the answer. Using stacks like this,
Since data can be input and output at high speed, the whole process is also speeded up.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to Examples. FIG. 1 shows an embodiment of the device of the present invention. The sequence controller 42 includes an instruction address generator 43, a decoder.
44, a bit register 45, a gate 46, etc. The instructions are composed of the format shown in FIG. 2. Among the instructions output from the instruction memory 1 to the instruction bus 50, the code is sent to the decoder 44 via the bus 51 and the address (PIO address) of the process input / output device is It is output to the process input / output device 2 via the bus 52. The bus 54 is a bus for exchanging data between the process input / output device 2 and the bit register 45.

Next, the operation of this embodiment will be described. For instruction reading, the address update signal 56 is output from the decoder 44, and the instruction address generator 43 receiving the address update signal 56 outputs the address of the instruction to be executed onto the instruction address bus 53. Then, the code part of the instruction read from the instruction memory 1 becomes
The PIO address is sent to the decoder 44 via the bus 51, and the PIO address is output to the process input / output device 2 via the bus 52. When the process input / output device 2 receives this address and the read signal 57 from the decoder 44, the corresponding data is transferred to the bus.
Read out on 54, this data is set in bit register 45 by latch signal 59 from decoder 44.

Data is written to the process input / output device 2 by a decoder.
By outputting the gate-on signal 60 from 44, the gate 46
Is turned on to output data on the bus 54, and then the decoder 44 outputs a write signal 58 to write the data on the bus 54 to the process input / output device 2 for execution.

The above is the operation of the present embodiment. The basic sequence processing executed by them is as follows, as shown in FIG. 3, because of the difference in the instruction and the contents of the bit register 45.
It is one of the three types of (a), (b), and (c).
That is, (a) the instruction is read, the data is read from the process input / output device according to the PIO address, and the data is set to the bit register D _r . (B) Only the instruction is read.
(C) Either read the instruction and write the contents of the bit register D _r to the process input / output device according to the PIO address.

A processing method based on these basic sequence processing will be first described with reference to FIGS. 10 to 13 used in the conventional example.
Since instruction I1 in FIG. 10 is a read command (LD), the processing of FIG. 3, regardless of the value of bit registers D _r (it) is performed. This is steps 1101 and 1102 in FIG. 11 (b). Since the next instruction I2 is an AND instruction, the processing differs depending on the value D _r of the bit register 45. That is, when D _r = 0 (this can be determined immediately when the instruction is read because the value D _r of the bit register 45 is given to the decoder 44 via the bus 55). The process of (b), that is, the process that ends only by reading the instruction, is the third when D _r = 1.
The processing of FIG. This is steps 1110 and 1105 in FIG. 11 (b), whereby the answer of the AND processing is set in the bit register 45. Fig. 10 Last instruction
Since I3 is writing (ST), the processing of FIG.
That is, steps 1107 and 1109 of FIG. 11 (b) are executed,
The AND processing answer is written to the address PIO3.

As is apparent from comparison between FIG. 11 (b) and FIG. 11 (a), the AND operation processed in 9 steps in the conventional method can be processed in 5 or 6 steps in this embodiment, and the number of steps is reduced. The processing can be speeded up by the amount.

Also in the case of the OR processing in FIG. 12, it is easily understood that the processing in FIG. 13 (b) is processed by applying FIG. 3, and the speed can be increased as in the case of the AND processing.

FIG. 4 is an example of a sequence including both AND and OR, and the value of each address of the process input / output device 2 is as follows: (PIO11) = 1 (PIO12) = (PIO13) = 0 When this sequence processing is carried out by the embodiment shown in FIGS. 1 and 3, it becomes as follows. First, since the instruction I11 is a read instruction, the processing shown in FIG. 3A is performed, and the value "1" of the address PIO11 is stored in the bit register 45 (steps 501 and 502 in FIG. 5). The next instruction I12 is an OR instruction, and since the content of the bit register 45 is "1" at this time, the processing (step 503) of FIG. 3B is performed, and the processing proceeds to the next instruction. The instruction I13 is an AND instruction, and the content of the bit register at this time is 1. Therefore, the processing is as shown in FIG. 3A, and the value "0" of the address PIO13 is stored in the bit register 45 (steps 504, 505). . Since the instruction I14 is a write instruction, the processing shown in FIG. 3C is performed, and the content "0" of the bit register 45 is written to the address PIO14 (steps 506 and 507). By the above processing, (PIO1
4) = ((PIO11) + (PIO12)). (PIO13) The calculation result is obtained in 7 steps of FIG. This is 12 steps with 4 instructions in the conventional method.
It shows that it is significantly faster.

FIG. 6 shows another embodiment of the present invention. The sequence controller 3 includes an address register 10, an instruction register 11, a decoder 12, a micro program address generator 13, a micro program memory 14, and a controller 15. An instruction address generator 16, a bit register 17, a stack 18, a gate 19, and control signals 21 to 30.

The instruction register 11 stores the instruction read from the instruction memory 1, outputs the instruction code among the stored instructions to the decoder 12 via the bus 33, and outputs the process input / output device address to the bus 37, the address register. 10, output to the process input / output device 2 via the address bus 4. decoder
12 is the instruction code and the contents and stack of the bit register 17.
The contents of 18 are analyzed to determine the start address of the microprogram to be executed, and it is output to the microprogram address generator 13. The micro program address generator 13 has both an address counter function and a jump destination address latch function, and outputs a micro program address onto the bus 35. The micro program memory 14 outputs a micro program on the bus 36, and the micro program goes through the controller 15 and the control signals 21 to 21.
30 and control each device. Instruction address generator 16
Outputs the address of the instruction to be executed, and the output instruction address is the bus 37, address register 1
0, output to the instruction memory 1 via the address bus 4. The bit register 17 stores the data read from the process input / output device 2, and the gate 19 outputs the contents of the bit register 17 to the process input / output device 2. The stack 18 is for temporarily saving the contents of the bit register 17.

FIG. 7 shows the basic sequence processing in this embodiment, and any one of the six types (d) to (d) is executed. These are (d) instruction read, bit register contents
Transfer D _r to stack 18 (S _r ), read from process I / O device to bit register, (e) instruction read, read from process I / O device to bit register, (to) instruction read only, (g) Instruction read, to bit register 1
The excisional, (h) instruction read, excisional 0 to bit register, (re) instruction read, write to the process input and output device contents D _r of bit registers, 6 kinds, which in Become types of instructions, the contents of the bit register D _r, determined by the contents of S _r of Sutatsuku. Contents of bit register 17 D _r is signal
31 and the contents S _{r of the} stack 18 as a signal 37 and the code in the instruction register is provided as a signal 33 to the decoder 12, so that the decoder 12 will be at the step when the read instruction is set into the instruction register 11. It can be determined which of these is to be executed.

The operation of this embodiment will be described by taking the sequence of FIG. 8 as an example. In the figure, (PIO21) = 0 (PIO22) = 1 (PIO23) = 0 (PIO24) = (PIO25) = (PIO27) = 1. Since the instruction I21 is a read instruction (LD), the seventh
The process shown in Fig. (D) is performed, and the bit register 17 (PIO2
1) = 0 is set (steps 901 to 903 in FIG. 9).
However, at this time, the contents S _{r of the} stack 18 are indefinite. However, the processing differs depending on the contents S _r of the stack 18 only in the case of the later special and the later special, and these two instructions are after the read instruction is executed twice or more due to the configuration of the sequence processing. Only appears. If the read command is executed more than once, the content S _{r of the} stack 18 is definitely determined and no problem occurs. Now, the next instruction I22 is an AND instruction, and at this time, the content of the bit register 17 is D _r
Therefore, only (f) processing is required (step 90
4) Go to the next instruction I23. Since this instruction is a read instruction, the processing becomes (d), the contents 0 of the bit register 17 is saved in the stack 18, and then (PIO23) = 0 is set in the bit register 17 (steps 905 to 907). .
Instruction I24 is an OR instruction, and at this time, bit register 17
Since the content D _{r of} 0 is 0, the processing of (e) is performed, and (PIO24) = 1 is set in the bit register 17 (steps 908 and 909). The instruction I25 is an AND instruction, and at this time, the content D _r of the bit register 17 is 1, so the processing in (e) is performed again, and the bit register 17 has (PIO25).
= 1 is set (steps 910 and 911). Order I26 is or special. Since this instruction is intended to excisional the result to the contents S _r and bit register contents D by calculating the OR of the _r D _r of Sutatsuku a _{D r = 1, S r =} 0 in this case, ( The process of (f) is performed (step 912) and the process proceeds to the next command. Since instruction I27 is and instruction, a content D _r = 1 in this case bit register 17 becomes a process of (e), the bit register 17 (PIO27) = 1 is excisional (step 913 and 914). Since the instruction I28 is a write instruction, it is the processing of (i), and the contents of the bit register 17 D _r
= 1 is written to address PIO28 (steps 915,91
6). When the above processes are summarized, the same result as when the following calculation is executed is obtained.

(PIO28) = ((PIO21)-(PIO22) + ((PIO23) + (PIO24))-(PIO25))-PIO27 In this example, the conventional method uses 8 instructions I21 to I28, each with 3
A total of 24 steps are required because of the need of steps, but in the present embodiment, the processing is completed in 16 steps as shown in FIG. 9, and the processing speed is increased.

In the sequence shown in FIG. 8 above, the AND-SPECIAL is not used, but this instruction is the same as the OR-SPECIAL.
The value S _r saved to the stack 18 and the value D _{r of the} bit register 17
This is for the purpose of speeding up the data transfer, etc. by saving the previously obtained calculation result in the stack.

Further, in the present embodiment, the sequence processing is configured to be executed by the microprogram, but the operation principle of the present invention is the same even when the sequence processing is executed by hardware, and it is obvious that the same effect is obtained. is there. Further, although the two embodiments described above show examples of the sequence controller that executes the 1-bit sequence operation, even when the sequence controller having both the 1-bit sequence operation function and the word operation function is executed. It is clear that the operating principle of the present invention is the same and the same effect is obtained.

〔The invention's effect〕

According to the present invention, it is possible to eliminate the need for a logical operation and the need to read out data from the process input / output device depending on the conditions. Therefore, the sequence processing can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the format of instructions, FIG. 3 is a diagram showing a basic sequence processing in the embodiment of FIG. 1, and FIG. 4 is a sequence processing. FIG. 5 is a process flow chart when the sequence of FIG. 4 is processed by the embodiment of FIG. 1, FIG. 6 is a configuration diagram showing another embodiment of the present invention, and FIG. Is a diagram showing a basic sequence process in the embodiment of FIG. 6, FIG. 8 is a diagram showing an example of the sequence process, and FIG. 9 is a process when the sequence of FIG. 8 is processed by the embodiment of FIG. Flow charts, FIGS. 10 and 11 are diagrams showing an AND operation sequence and its processing flow, and FIGS. 12 and 13 are diagrams showing an OR operation sequence and its processing flow. 1 ... Instruction memory, 2 ... Process input / output device, 3, 42 ...
… Sequence controller, 12,44 …… Decoder, 17,45
… Bit register, 18… Stack.

Claims (4)

[Claims] 1. When a data read command having an address of a first process target data is received from a command memory storing a command for sequence control of a process, the first process is performed from the address of the process input / output device. The target data is read out and set in a register provided for processing work to finish the processing of the instruction, and the AND instruction having the address of the second processing target data is received from the instruction memory and set in the register. Value is 0
Or when the OR instruction having the address of the second processing target data is received from the instruction memory and the value set in the register is 1, the instruction is not read out without reading the second processing target data. When the AND instruction having the address of the second data to be processed is received from the instruction memory and the value set in the register is 1, or the second data to be processed from the instruction memory is processed. The OR instruction having the address is received and the value set in the above register is 0.
In the case of, the second data to be processed is read from the address of the process input / output device, is set in the register to end the processing of the instruction, and when the write instruction having the write address is received from the instruction memory. A sequence control processing method characterized in that the value of the register is transferred to the write address of the process input / output device to terminate the processing of the instruction. 2. A stack for saving the intermediate processing result is provided: When the data read command is received from the command memory, the value of the register is first transferred to the stack and then the address of the process input / output device is set. When the first and second data to be processed are read from the above, are set in the register to finish the processing of the instruction, and when the special and instruction is received from the instruction memory,
When the value of the register is 1 and the value of the stack is 0, the value of the register is set to 0, and otherwise the processing of the instruction is ended and the special or instruction is received from the instruction memory. If the value of the register is 0 and the value of the stack is 1, the value of the register is set to 1, and otherwise the processing of the instruction is terminated without doing anything. A processing method of sequence control according to claim 1. 3. Instruction reading means for reading an instruction for sequence control of a process from an instruction memory, a register, a data transfer means for transferring data between the register and a process input / output device, and a control means. When receiving a data read command having the address of the first process target data from the command memory, the first process target data is read from the address of the process input / output device and set in the register. Ends the processing of the instruction, receives the AND instruction having the address of the second data to be processed from the instruction memory and the value set in the register is 0, or the second processing from the instruction memory. When the OR instruction with the address of the target data is received and the value set in the above register is 1. The second processing target data end the processing of the instruction without reading the value that is excisional the second processing target and instructions are received and the register having the address of the data from the instruction memory 1
Or when the OR instruction having the address of the second data to be processed is received from the instruction memory and the value set in the register is 0, the second data to be processed is stored in the process input / output device. The value of the register is read from the address by the data transfer means, set in the register to finish the processing of the instruction, and when the write instruction having the write address is received from the instruction memory, the value of the register is stored in the process input / output device. A sequence control processing device characterized in that the data transfer means transfers the instruction to the write address to end the processing of the instruction; the control means has a function. 4. A stack for saving the intermediate processing result is provided: When the data read command is received from the command memory, the value of the register is first transferred to the stack and then the address of the process input / output device is set. When the first and second data to be processed are read from the above, are set in the register to finish the processing of the instruction, and when the special and instruction is received from the instruction memory,
When the value of the register is 1 and the value of the stack is 0, the value of the register is set to 0, and otherwise the processing of the instruction is ended and the special or instruction is received from the instruction memory. When the value of the register is 0 and the value of the stack is 1, the value of the register is set to 1, and otherwise the processing of the instruction is terminated; the control means has the function. The sequence control processing device according to claim 3, wherein the processing device is a sequence control device.