JP2826781B2 - Data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system,
The present invention relates to a data transfer method in which a channel device controlled by a channel control device transfers data with a peripheral device.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional data transfer device.

[0003] The conventional example shown in FIG.
, An operational out (OPO) F / F11, a data buffer pointer 12, and a read / write flag F
/ F13 and a transfer control unit 14. Here, when performing the return operation, the channel control device 1B
Resets the OPOF / F11 to “0” and sets the peripheral device 3
The logical connection between B and channel 2 is disconnected, and data transfer is started.

When performing a write transfer, the channel controller 1B sets the read / write F / F 13 to the write side, and the data buffer pointer 12 sets the buffer to an empty state. Start a data request to 1B. The channel control device 1B reads data from a memory (not shown) and sends the data to the channel device 2B. The transfer control unit 14 stores the data in the data buffer 10 and updates the buffer pointer 12. The data request is executed until the buffer pointer 12 fills the buffer, at which point the operation stops.

When performing a read transfer, the channel controller 1B sets the read / write F / F 13 on the read side, and the data buffer pointer 12 sets the buffer to a full state. The data in the data buffer 10 is read from 1B and a data request is started. Channel control device 1
B stores data in a memory (not shown) and sends the number of received bytes to the channel device 2B. The transfer control unit 14 updates the buffer pointer 12, executes the data request until the data buffer 10 becomes empty, and stops the operation when it becomes empty.

[0006]

This conventional data transfer device has a channel return function so that a data transfer function can be performed without using a peripheral device as a means of design evaluation after trial production and function confirmation after repair. I had. In this channel return method, the internal state of the channel device is manipulated by the channel control device, and data transfer is forcibly performed. Therefore, transfer exceeding the data buffer amount of the channel cannot be performed. Also, since the channel device cannot notify the channel controller of the transfer end, the channel controller must recognize the transfer end by a method such as timer monitoring. Further, there has been a problem that operations other than data transfer cannot be confirmed.

[0007]

A data transfer method according to the present invention is a data transfer method in which a plurality of channel devices controlled by a channel control device transfer data with peripheral devices via an I / O interface. The device includes a designation unit for instructing switching of the channel operation mode, a control table storing a plurality of bytes of information for simulating the control information and the input information of the I / O interface, and a designation of the return mode by the designation unit. A switching means for disconnecting the I / O interface, a computing means for subtracting one output from a register for setting one byte of initial data, and a control means for reading the control information when a read transfer is instructed. Transfer means for transferring a predetermined byte to the register and sending out the output of the arithmetic means as read data. That.

[0008]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.

In response to an instruction from the channel control device 1A, the channel device 2A controls the operation of the I / O interface with the peripheral device 3B. The channel device 2A includes a control table 20 and a control table reading register 21.
A register 22 for storing an initial value of the register 21;
An arithmetic unit 23 for subtracting -1 from the output of the register 22, a comparator 27 for comparing the outputs of the arithmetic unit 23 and the data buffer 10, a determining unit 31 for determining whether or not the output of the arithmetic unit 23 is all 0; A status register 28 for storing the result of the comparator 27, a control unit 35 for controlling the decoding and transfer control of the control information in the register 21 for reading out the control table and an interrupt to the channel control device, and a timing generation for generating timing A circuit 29; a log buffer 34 for storing log information inside the channel device 2;
A strobe signal control circuit 30 for switching between a strobe signal from the CPU and an output of the timing generation circuit 29;
OPOF / F11 for holding an OPO signal to A, and register 3 for temporarily storing bus-in information from peripheral device 3A
2, a selector 24 for switching between the output of the arithmetic unit 23 and the output of the log buffer 34, a selector 25 for switching between the output of the selector 24 and the output of the bus interface 32,
A selector 26 for switching the output of the selector 25 and the write data from the channel control device 1A and outputting the data to the data buffer 10, the output of the bus-in register 32, the output from the status register 28, and the output of the register 21 for reading the control table. To switch channel control device 1
And a selector 33 for sending out to A.

FIG. 3 is a diagram showing control information stored in the control table 20 of this embodiment. Each word is composed of 8 bytes, byte 0 is a command, byte 1 is a flag, and byte 2 is an initial value. An initial value set in the register 22,
Bytes 3 to 7 are data corresponding to information read in the service code sequence from the peripheral device 3A. The command in byte 0 instructs the control unit 35 on the length of the service code sequence. The flag of byte 1 complements the operation of channel device 2A, and each bit has a meaning. Bit 0 reads out and executes the control information of the next address of control table 20 when channel 2 becomes idle. Bit 2 is a compare designation. When write data transfer is instructed by the channel control device 1A, the output of the data buffer 10 is compared with the output of the arithmetic unit 23, and the result is stored in the status register 28.
If they do not match, the status of the register in the channel device 2A is saved in the log buffer 34. Bit 3 instructs the lower end, and during execution of data transfer, the judging means 31
When the output of No. 3 detects all 0s, the data transfer is terminated. Bit 4 indicates data replacement, replacing the data in control information byte 6 with status register 28.
Bit 5 indicates a log, and when the read data transfer is instructed from the channel controller 1A, the output of the log buffer 34 is stored in the data buffer 10 instead of the output of the arithmetic unit 33. Bits 6 and 7 indicate the transfer speed, and indicate to the timing generation circuit 29 the generation cycle of the strobe signal.

Next, the operation of this embodiment will be described. The channel control device 1A instructs the channel device 2A to perform the return mode, sets the register 11 to "0", and disconnects the logical connection with the peripheral device 3A. That is, thereafter, a change in the I / O interface signal has no effect on the channel device 2A and the peripheral device 3A except for the OPO signal.

Next, the channel control device 1A prepares control information corresponding to the service code sequence to be simulated and stores it in the control table 20. Next, when the channel control device 1A executes the channel program corresponding to the service code sequence sequence, the channel control device 1A instructs the control unit 35 to start. The control unit 35 immediately enters the control table 2
The first data of 0 is stored in the control table read register 21.
And decode the command part of byte 0. When the command section indicates a service code (SC) sequence, the information (SC) in byte 3 of the register 21 for reading the control table is determined, and a service code interrupt is generated for the channel controller 1A. The channel control device 1A decodes the contents of the service code through the selector 33 and performs a predetermined operation.

In read transfer, in the case of a service code instructing read data, the channel controller 1A mainly designates data to be transferred from the channel device 2A by a data address based on a data address and a byte count of a channel program to be executed. The operation of storing the data at the address of the memory is executed. Here, the channel control device 1A gives a byte count to the control unit 35 and issues a read data transfer instruction. The control unit 35 that has received the read transfer instruction sets the initial value data of the byte 2 of the control table read register 21 in the register 22 of the initial value data. Further, the generation speed of the strobe signal is instructed to the timing generation circuit 29 by the bits 6 and 7 of the flag portion of the byte 1.

A timing generation circuit 29 generates a strobe signal at a designated cycle, and outputs a strobe signal control circuit 3
Send to 0. The strobe signal control circuit 30 outputs the output of the arithmetic unit 23 to the data buffer 10 through the selector 24, the selector 25 and the selector 26 every time a strobe is detected.
And the register 22 is updated. At the same time, the control unit 35 updates the byte count provided by the channel control device 1A based on the output from the strobe signal control circuit 30, and continues the operation until it becomes "0".
The data stored in the data buffer 10 is transferred to the channel control device 1A and stored in the main storage device.
Thus, the read data transfer operation is executed in the channel return mode.

In the write data transfer, similarly to the read data transfer, in the case of the write data transfer, the channel control device 1A gives a byte count to the control unit 35 and instructs the write transfer. The control unit 35 determines the state of the data buffer 10 and issues a data request to the channel control device 1A if there is a free space. The channel control device 1A reads data from the main memory address designated by the channel program and sends the data to the channel device 2A. The channel device 2A stores the write data in the data buffer 10 through the selector 26. Further, the control unit 35 instructs the timing generation circuit 29 on the generation speed of the strobe signal by the bits 6 and 7 of the flag byte. The timing generation circuit 29 generates a strobe signal at the designated cycle and sends it to the strobe signal control circuit 30. The strobe signal control circuit 30 reads data from the data buffer 10 every time a strobe signal is detected. The data read at this time is picked up by the channel device 2A. Further, the control unit 30
Updates the byte count given from the channel control device 1A every time a strobe signal is generated, and this operation is continued until the byte count becomes zero.

At the lower end, in both the read transfer and the write transfer, the initial value of byte 2 of the control table read register 21 is updated by -1 each time a strobe signal is generated using the register 22 and the arithmetic unit 23. If bit 3 of the flag byte indicates lower end, the determination circuit 31 determines the output of the arithmetic unit 23,
Is detected, an all 0 detection signal is sent to the control unit 35. The control unit 35 terminates the data transfer by this signal. That is, the data transfer can be completed before the byte count given from the channel control device 1A becomes zero.

In the write compare, if the compare is designated by bit 2 of the flag byte at the time of write data transfer, the data read from the data buffer 10 and the output of the arithmetic unit 23 are compared by the comparator 27 and the result is compared. It is stored in the status register 28. Further, if they do not match, the state of the register inside the channel device 2A is stored in the log buffer 34.

In the log transfer, when the log transfer is instructed by the flag byte bit 5 of the read transfer, the selector 24 uses the output of the log buffer 34 as read data instead of the output of the arithmetic unit 23 through the selectors 25 and 26. The data is stored in the data buffer 10. Thereby, the channel control device 1A can read the log information of the channel device 2A.

In the status transfer, if there is a status read instruction from the channel control device 1A, the control unit 35 determines the command of byte 0 of the register 21 for reading the control table. If it is 14 (16), bytes 5, 6 and 15 (16) are sent to the channel controller 1A as bytes 5, 6, 7 as status. Thereby, the status transfer can be performed in a pseudo manner.

In the data replacement, when the flag byte bit 4 of the status transfer operation indicates data replacement, the selector 33 replaces the byte 6 of the control table read register 21 with the status register 28 by using the channel controller 1A. Send to Thereby, the channel control device 1A can know the result of the previous write data compare.

[0021]

As described above, according to the present invention, the channel return operation is instructed by the control table, so that the read data transfer, the write data comparison, the lower end operation, and the log information transfer can be performed without using a peripheral device. The reading of the comparison result and the data transfer operation by changing the data transfer speed can be performed as if a normal channel program is executed.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of an example of a conventional data transfer device.

FIG. 3 is a diagram illustrating information of a control table according to the present embodiment.

[Explanation of symbols]

 Reference Signs List 1A channel control device 2A channel device 3A peripheral device 10 data buffer 11 operation mode switching (OPOF / F) 12 buffer pointer 13 read / write F / F 14 transfer control unit 20 control table 21, 22, 28, 32 register 23 arithmetic unit 24 , 25, 26, 33 selector 27 comparator 29 timing generation circuit 30 strobe signal control circuit 31 determination means 34 log buffer

Claims (7)

(57) [Claims] 1. In a data transfer system in which a plurality of channel devices controlled by a channel control device transfer data to a peripheral device via an I / O interface, the channel device designates switching of a channel operation mode. A control table in which a plurality of bytes of information simulating the control information and input information of the I / O interface are stored; and when the return mode is designated by the designation means, the I / O interface is disconnected. Switching means, an operation means for subtracting one from the output of a register for setting one byte of initial data, and transferring a byte defined in the control information to the register when read transfer is instructed, and Transfer means for sending output of the means as read data. 2. The channel device further comprises timing generation means for outputting a pulse at a specified interval.
2. The data transfer method according to claim 1, wherein an update timing of said arithmetic means is changed according to a transfer speed instruction of control information of said control table. 3. The channel device further comprises an all 0 determining means, and when the control information of the control table indicates lower end, when the output of the arithmetic means is detected as all 0, data transfer is performed. 3. The data transfer method according to claim 2, wherein 4. The channel device is provided with 1-byte comparing means and status storing means, and compares the output of the calculating means with the write data when the control information of the control table specifies data comparison. 4. The data transfer method according to claim 3, wherein the result is set in a status storage unit. 5. The channel device further comprises a selection unit for switching between an output of a log storage unit in the own channel and an output of the arithmetic unit, and an output of the storage unit when control information of the control table is a log transfer instruction. 5. The data transfer method according to claim 4, wherein the data is transferred as read data. 6. When the control information in the control table indicates a status transfer from the peripheral device, the channel device stores a predetermined byte in the control table as status information from the peripheral device. The data transfer method according to claim 6, wherein 7. The status register according to claim 6, wherein the channel device replaces a part of the status information in the control table with the status register when the control information of the control table specifies data replacement. Data transfer method.