JPS59168999A - Memory monitoring circuit - Google Patents

Abstract

PURPOSE:To read the contents of a memory freely in a system in which interruption of program execution is not allowed by providing second memory having the same address with a system memory and writable from a common bus and a device that reads out the second memory. CONSTITUTION:A memory 4 has the same address with a memory 3. It monitors the system and only writing is possible from a common bus. A system monitoring device 5 reads the memory 4 and analyses and displays the contents. In ordinary operation of the system data are exchanged between a CPU1 and the memory 3 through the common bus. As the memory 4 is the same address with the memory 3, the same data with the memory 3 are written. Accordingly, the contents of the memory 3 and memory 4 are always the same, and therefore, the contents of the memory 3 can be known by looking the contents of the memory 4. Accordingly, by reading the contents of the memory 4 by the monitoring device 5 when writing is not made in the memory 4, the memory can be monitored without stopping the system.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory monitoring circuit, and more particularly, to a memory monitoring circuit that monitors and controls the state of an operating memory in a system in which interruption of program execution is not allowed, and detects and analyzes abnormal system operation based on the monitoring and control. This invention relates to a memory monitoring circuit suitable for

Conventionally, in order to know the contents of a computer's memory, it was necessary to interrupt a running program and perform a read operation. Therefore, memory monitoring has been impossible in systems where interruption of program execution is not allowed.

The present invention has been made in view of the above-mentioned conventional circumstances.
Therefore, an object of the present invention is to provide a novel memory monitoring circuit that can freely read the contents of memory in a system where interruption of program execution is not allowed.

In order to achieve the above object, a memory monitoring circuit according to the present invention includes an operating system memory connected to a common bus, a system memory having the same address as the system memory, and a memory monitoring circuit connected to the common bus. The system comprises a second memory that can only be written to from a common bus, and means for monitoring the system memory during operation by reading and analyzing the second memory.

Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, reference number 1 indicates the central processing Mt of the system.
(CPU), 2 is a common bus of the system, 3 is a memory of the system, and 4 is a memory having the same address as memory 3 and for monitoring this system;
Only writing is possible from the common bus 2. 5 is memory 4
This is a system monitoring device that reads out, analyzes and displays the contents.

In the normal operation of the system, data is transferred between the CPU 1 and memory 3 via the common bus 2, but since memory 4 also has the same address as memory 3, the same data as memory 3 is written. .

Therefore, since the contents of memory 3 and memory 4 are always the same, the contents of memory 3 can be known by looking at the contents of memory 4. Therefore, by having the monitoring device 5 read the contents of the memory 4 when no data is being written to the memory 4, the memory can be monitored without stopping the system.

The present invention is configured and operates as described above.According to the present invention, data in memory can be read and analyzed without affecting the operating system, so abnormal system operation can be discovered. , the analysis becomes easier.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1φ- Central processing unit (CPU), 2... Common bus,
3. System memory, 4. Memory that can only be written to from common node 2 and has the same address as memory 3, 5. System monitoring device that reads and analyzes music and memory 4 Patent applicant Japan Denki Co., Ltd. Representative Patent Attorney Yutabe Kumagai

Claims (1)

[Claims] operating system memory connected to a common bus;
a second memory that has the same address as the system memory and is connected to the common bus and can only be written to from the common bus; and a second memory that is in operation by reading and analyzing the second memory. A memory monitoring circuit comprising means for monitoring system memory.