[go: up one dir, main page]

JPH0215749A - System for setting line controlling information for communication control processor - Google Patents

System for setting line controlling information for communication control processor

Info

Publication number
JPH0215749A
JPH0215749A JP63164897A JP16489788A JPH0215749A JP H0215749 A JPH0215749 A JP H0215749A JP 63164897 A JP63164897 A JP 63164897A JP 16489788 A JP16489788 A JP 16489788A JP H0215749 A JPH0215749 A JP H0215749A
Authority
JP
Japan
Prior art keywords
line
processor
communication control
control information
controlling information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63164897A
Other languages
Japanese (ja)
Other versions
JPH07121021B2 (en
Inventor
Hideaki Yano
夜野 英昭
Yasushi Okada
岡田 靖史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP63164897A priority Critical patent/JPH07121021B2/en
Publication of JPH0215749A publication Critical patent/JPH0215749A/en
Publication of JPH07121021B2 publication Critical patent/JPH07121021B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Communication Control (AREA)

Abstract

PURPOSE:To automatically produce line controlling information by providing line attribute displaying registers which display attributes of lines to line adapters and reading out and storing in a memory contents of the registers by a program at the time of initializing a communication control processor. CONSTITUTION:A processor 3 produces line controlling information 21 required for controlling a line to be housed in a line interface section 41 in a memory 2 based on the content of a line attribute displaying register 51. Then the processor 3 reads out the content of the line attribute displaying register 52 corresponding to a line interface section 42 and produces the line controlling information 21 of the section 42. Thus the processor 3 produces the line controlling information 21 of all line interface sections by reading out the line attribute displaying registers of all line adapters in a communication control processor. When it becomes necessary to use the line interface section 43 of an unused line, the processor changes the value of a line attribute displaying register 53 to the attribute of a used line and produces the line controlling information 21 and, at the same time, informs the host device 7 of the communication control processor of the change.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、通信制御処理装置における、回線制御に必要
な回線制御情報の設定方法に関するものであって、収容
する回線の属性が変化した場合に、変化した属性を読み
取り、回線制御情報を自動作成する通信制御処理装置の
回線制御情報設定方式に関するものである。
[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a method for setting line control information necessary for line control in a communication control processing device, and the present invention relates to a method for setting line control information necessary for line control in a communication control processing device. The present invention relates to a line control information setting method for a communication control processing device that reads changed attributes and automatically creates line control information.

(従来の技術) 通信制御処理装置では、収容される各回線毎に、回線速
度、回線インタフェース等の回線属性をメモリ上に回線
制御情報として取りまとめ、その情報を使用して、回線
速度、回線インタフェース等の情報を各回線アゲブタ(
LA)に初期設定するとともに、情報に設定された回線
種別に応じて、信号線監視・制御、データ送受信制御等
を行っている。装置により収容する回線の種別、回線数
が異なるため、回線制御情報は装置ごとに異なっている
。このため、この情報は、装置毎に予めシステムジェネ
レーション(SG)により作成していた。
(Prior Art) A communication control processing device compiles line attributes such as line speed and line interface for each accommodated line as line control information in memory, and uses this information to determine the line speed and line interface. Information such as each line Agebuta (
In addition to performing initial settings on the LA), signal line monitoring and control, data transmission and reception control, etc. are performed according to the line type set in the information. Since the types of lines and the number of lines accommodated differ depending on the device, the line control information differs depending on the device. For this reason, this information has been created in advance for each device by system generation (SG).

(発明が解決しようとする課題) したがって、収容する回線の種類、収容回線数が変更に
なると再度システムジェネレーションを行い、回線制御
情報を作成し直す必要があり、これら変更に柔軟に対処
できないという問題があった。
(Problem to be solved by the invention) Therefore, when the type of line to be accommodated or the number of lines to be accommodated changes, it is necessary to perform system generation again and recreate the line control information, and the problem is that it is not possible to deal with these changes flexibly. was there.

本発明の目的は、通信制御処理装置に収容する回線速度
、回線インタフェース等の回線属性を変更する必要が生
じた場合でも、再度のシステムジェネレーションを不要
とし、これら変更に柔軟に対処可能とすることである。
An object of the present invention is to eliminate the need for another system generation even if it becomes necessary to change line attributes such as line speed and line interface accommodated in a communication control processing device, and to be able to deal with these changes flexibly. It is.

(課題を解決するための手段) 前記目的を達成するための本発明の特徴は、通信回線と
上位装置の間に位置し、回線制御に必要な回線制御情報
を格納するメモリと、回線を接続・収容する回線アダプ
タと、該回線アタックを制御して回線の信号線監視・制
御及びデータ送受信制御を行うプロセッサとを有し、回
線制御情報に基づいて回線を制御する通信制御処理装置
において、前記回線アダプタが回線属性を記憶する回線
属性表示レジスタを具備し、前記回線アタックにお&ツ
る回線属性の変化を認識する回線属性変更認識部からの
通知に基づき、プロセッサにより回線属性を読み込み前
記メモリ上に回線制御情報を設定し、該メモリの内容を
上位装置が読み取る、通信制御処理装置における回線制
御情報設定方式にある。
(Means for Solving the Problems) A feature of the present invention for achieving the above-mentioned object is a memory that is located between a communication line and a host device and stores line control information necessary for line control, and a memory that connects the line. - A communication control processing device that has a line adapter to accommodate and a processor that controls the line attack and monitors and controls the signal line of the line and controls data transmission and reception, and controls the line based on line control information. The line adapter is equipped with a line attribute display register that stores line attributes, and based on a notification from a line attribute change recognition unit that recognizes changes in line attributes due to the line attack, the processor reads the line attributes into the memory. This is a method for setting line control information in a communication control processing device, in which line control information is set on the top of the memory, and the contents of the memory are read by a host device.

(作用) 従来、通信制御処理装置では、各回線毎の回線属性をと
りまとめた回線制御情報を使用し回線を制御している。
(Function) Conventionally, communication control processing devices control lines using line control information that compiles line attributes for each line.

回線制御情報は装置毎に異なるため、装置の提供者は、
予めシステムジェネレーションにより回線制御情報を作
成していた。
Since line control information differs depending on the device, the device provider
Line control information was created in advance through system generation.

本発明は、回線アゲブタに回線属性を表示する回線属性
表示レジスタを設け、通信制御処理装置の初期化時に、
プログラムによって回線アタックの回線属性表示レジス
タ内容を読み出し、メモリに格納することによりプログ
ラムにより回線制御情報を自動生成可能とする。
The present invention provides a line attribute display register for displaying line attributes in a line adapter, and when initializing a communication control processing device,
By reading the contents of the line attribute display register for line attack using a program and storing it in the memory, line control information can be automatically generated by the program.

又、回線属性表示レジスタの内容に変更があったときは
、プロセッサへの割込動作により、その内容をメモリに
格納する。又上位装置にも割込みをかけて、内容に変化
のあったことを通知する。
Furthermore, when the contents of the line attribute display register are changed, the contents are stored in the memory by interrupting the processor. It also interrupts the host device to notify it that there has been a change in the content.

(実施例) 第1図に本発明の一実施例を示す。第1図において、■
は回線を収容・制御する通信制御処理装置、2は回線制
御情報を格納するメモリ、21は回線制御情報、3は回
線アダプタを制御するプロセッサ、41,42,43.
44は回線インタフェース部、5は回線インタフェース
部41,42,43.44を収容する回線アダプタ、5
1.52.53.54はそれぞれ回線インタフェース部
41.42.43.44に対応する回線の属性を表示す
る回線アタック5内の回線属性表示レジスタ、6は回線
属性表示レジスタが変更されたことを認識するとともに
プロセッサ3に回線情報の作成を指示する回線属性変更
認識部、7は1の上位装置である。
(Example) FIG. 1 shows an example of the present invention. In Figure 1, ■
2 is a memory that stores line control information; 21 is line control information; 3 is a processor that controls a line adapter; 41, 42, 43 .
44 is a line interface section; 5 is a line adapter that accommodates the line interface sections 41, 42, 43, and 44;
1.52.53.54 are line attribute display registers in line attack 5 that display the attributes of the line corresponding to the line interface section 41.42.43.44, and 6 indicates that the line attribute display register has been changed. A line attribute change recognition unit 7, which recognizes the information and instructs the processor 3 to create line information, is a higher-level device of 1.

第1図を用い回線制御情報設定方式の動作例について説
明する。第1図において、プロセッサ3は、回線属性変
更認識部6の指示に従い、回線アダプタ5の内の回線属
性表示レジスタ51の内容を読み出す。プロセッサ3は
回線属性表示レジスタ51の内容に基づき、メモリ2に
回線インクフェース部41が収容する回線を制御するの
に必要な回線制御情報21の作成を開始する。回線イン
タフェース部41の回線制御情報21の作成が完了する
と次にプロセッサ3は同様に回線インクフェース部42
に対応する回線属性表示レジスタ52の内容を読み出し
、回線インタフェース部42の回線制御情報21を作成
する。このようにして、通信制御処理装置内の全回線ア
ダプタの回線属性表示レジスタを読み出しては回線制御
情報21の作成を行う。このとき、回線インクフェース
部43に収容する回線が未使用状態の場合には、回線属
性表示レジスタ53は回線未使用を表示しているため、
回線制御情報21の回線インタフェース部43に対応す
る領域のみ確保して空白として処理を続行する。
An example of the operation of the line control information setting method will be explained using FIG. In FIG. 1, processor 3 reads the contents of line attribute display register 51 in line adapter 5 in accordance with instructions from line attribute change recognition unit 6. Based on the contents of the line attribute display register 51, the processor 3 starts creating line control information 21 necessary for controlling the line accommodated in the line ink face unit 41 in the memory 2. When the creation of the line control information 21 of the line interface section 41 is completed, the processor 3 similarly creates the line ink interface section 42.
The contents of the line attribute display register 52 corresponding to the line attribute display register 52 are read out, and the line control information 21 of the line interface unit 42 is created. In this way, the line attribute display registers of all line adapters in the communication control processing device are read out to create line control information 21. At this time, if the line accommodated in the line ink face section 43 is unused, the line attribute display register 53 indicates that the line is unused.
Only the area corresponding to the line interface section 43 of the line control information 21 is reserved and processing is continued with it blank.

今、回線未使用の回線インタフェース部43を使用する
必要が生じた場合、回線属性表示レジスク53の値を使
用回線の属性に変更する。回線属性変更認識部6は回線
属性表示レジスタ53の値が変更されたことを認識し、
プロセッサ3に回線属性が変更されたことを通知する。
If it becomes necessary to use an unused line interface unit 43, the value of the line attribute display register 53 is changed to the attribute of the used line. The line attribute change recognition unit 6 recognizes that the value of the line attribute display register 53 has been changed,
The processor 3 is notified that the line attributes have been changed.

プロセッサ3は回線属性変更認識部6から回線インタフ
ェース部43の回線制御情報21を作成せよとの指示に
従い、先に値を変更した回線属性表示レジスタ53を読
み出すことにより、43に対応する回線制御情報21を
作成するとともに21が変更されたことを割込みにより
、通信制御処理装置の上位装置7に通知する。
The processor 3 follows the instruction from the line attribute change recognition unit 6 to create the line control information 21 of the line interface unit 43, reads the line attribute display register 53 whose value has been changed previously, and creates the line control information corresponding to the line attribute display register 53. 21 is created, and the host device 7 of the communication control processing device is notified of the fact that 21 has been changed through an interrupt.

上位装置7は、通信制御処理装置1から変更内容を受取
ることにより、7の処理に必要な制御情報の変更を行う
The host device 7 changes the control information necessary for the process 7 by receiving the change content from the communication control processing device 1.

回線属性表示レジスタ(51〜54)の各々は、例えば
17ビツト構成(ビット0〜ビツト16)で、その構成
の1例を第1表に示す。なお、伝送制御属性情報を回線
アダプタ5に持たせることにより、伝送制御情報21を
自動生成することが可能であることは云うまでもない。
Each of the line attribute display registers (51 to 54) has, for example, a 17-bit configuration (bit 0 to bit 16), and an example of the configuration is shown in Table 1. It goes without saying that by providing the line adapter 5 with transmission control attribute information, it is possible to automatically generate the transmission control information 21.

(発明の効果) 本方式によれば、通信制御処理装置に収容する回線の回
線種別、回線速度の変更、回線数の増減等が必要となっ
た場合でも、回線系の構成変更に柔軟に対応でき、また
、回線制御情報が変更されたことを上位装置に通知し、
上位装置の制御情報を動的に変更できるため、従来行っ
ていたシステムジェネレーション作業を不要と出来る。
(Effects of the Invention) According to this method, even if it becomes necessary to change the line type or line speed of the line accommodated in the communication control processing device, increase or decrease the number of lines, etc., it is possible to flexibly respond to changes in the line system configuration. It also notifies the higher-level device that the line control information has been changed.
Since the control information of the host device can be dynamically changed, the system generation work that was conventionally performed can be eliminated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による通信制御処理装置のブロック図で
ある。 l・・・・通信制御処理装置、 2・・・・メモリ。 3・・・・プロセッサ。 41.42,43.44・・・・回線インタフェース部
。 5・・・・回線アダプタ。 51.52,53.54・・・・回線属性表示レジスタ
。 6・・・・回線属性変更認識部。 7・・・・上位装置。
FIG. 1 is a block diagram of a communication control processing device according to the present invention. l...Communication control processing device, 2...Memory. 3... Processor. 41.42, 43.44...Line interface section. 5...Line adapter. 51.52, 53.54...Line attribute display register. 6...Line attribute change recognition unit. 7... Upper device.

Claims (1)

【特許請求の範囲】 通信回線と上位装置の間に位置し、回線制御に必要な回
線制御情報を格納するメモリと、回線を接続・収容する
回線アダプタと、該回線アダプタを制御して回線の信号
線監視・制御及びデータ送受信制御を行うプロセッサと
を有し、回線制御情報に基づいて回線を制御する通信制
御処理装置において、 前記回線アダプタが回線属性を記憶する回線属性表示レ
ジスタを具備し、 前記回線アダプタにおける回線属性の変化を認識する回
線属性変更認識部からの通知に基づき、プロセッサによ
り回線属性を読み込み前記メモリ上に回線制御情報を設
定し、該メモリの内容を上位装置が読み取ることを特徴
とする、通信制御処理装置における回線制御情報設定方
式。
[Scope of Claims] A memory located between a communication line and a host device and storing line control information necessary for line control, a line adapter for connecting and accommodating the line, and a memory for controlling the line by controlling the line adapter. A communication control processing device that includes a processor that monitors and controls signal lines and controls data transmission and reception, and controls the line based on line control information, wherein the line adapter includes a line attribute display register that stores line attributes; Based on a notification from a line attribute change recognition unit that recognizes a change in line attributes in the line adapter, a processor reads line attributes and sets line control information on the memory, and causes a host device to read the contents of the memory. A line control information setting method in a communication control processing device.
JP63164897A 1988-07-04 1988-07-04 Line control information setting method in communication control processor Expired - Lifetime JPH07121021B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63164897A JPH07121021B2 (en) 1988-07-04 1988-07-04 Line control information setting method in communication control processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63164897A JPH07121021B2 (en) 1988-07-04 1988-07-04 Line control information setting method in communication control processor

Publications (2)

Publication Number Publication Date
JPH0215749A true JPH0215749A (en) 1990-01-19
JPH07121021B2 JPH07121021B2 (en) 1995-12-20

Family

ID=15801945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63164897A Expired - Lifetime JPH07121021B2 (en) 1988-07-04 1988-07-04 Line control information setting method in communication control processor

Country Status (1)

Country Link
JP (1) JPH07121021B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019124275A1 (en) * 2017-12-21 2019-06-27 村田機械株式会社 Method for controlling communication system, communication system, and relay device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019124275A1 (en) * 2017-12-21 2019-06-27 村田機械株式会社 Method for controlling communication system, communication system, and relay device
CN111492631A (en) * 2017-12-21 2020-08-04 村田机械株式会社 Control method for communication system, and relay device
US11496336B2 (en) 2017-12-21 2022-11-08 Murata Machinery, Ltd. Method of a communication system having a control device and a relay device

Also Published As

Publication number Publication date
JPH07121021B2 (en) 1995-12-20

Similar Documents

Publication Publication Date Title
JPH0215749A (en) System for setting line controlling information for communication control processor
JPS5914005A (en) Sequence control method using microcomputer
JPS59168999A (en) Memory monitoring circuit
KR0157456B1 (en) User determined function of robot controller
JPS5839347A (en) Processor
JP2003186666A (en) Microcomputer and dma control circuit
JPH04148344A (en) Rom emulator
JPH06266630A (en) Input/output controller with trace function
JPS6349942A (en) Arithmetic processing unit
JPH03219342A (en) Programmable address conversion system
JPH01276241A (en) Multiple interrupting device
JPS62256139A (en) Data processor
JPH09128247A (en) Program conversion adapter
KR20010005141A (en) Interrup process method of pci adapter
JPS63318651A (en) Memory managing circuit
JPS62256138A (en) Data processor
KR19990058631A (en) DM Controller
JPS62238757A (en) Print control method
JPH01266642A (en) Memory controller
JPS62111326A (en) Man-machine interface device in data processor
JPH0272443A (en) Data processor
JPH01102643A (en) Data processing system
JPS63265338A (en) Program control system
JPS62130452A (en) Information processor
JPH02299004A (en) Monitor system for programmable controller

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071220

Year of fee payment: 12

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081220

Year of fee payment: 13

EXPY Cancellation because of completion of term
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081220

Year of fee payment: 13