JPH0354641A - Random memory monitor - Google Patents

Abstract

PURPOSE:To immediately and easily read out a memory content by always writing the same data as that in a random memory in an electronic circuit on an external memory. CONSTITUTION:A probe 1 is connected to the external memory 5 with the same capacity as that of the random memory targeted to be monitored via a buffer 2, and the buffer 2 comprises a buffering part 13 with a clock 3, and is connected to a read/write part 14 consisting of a control circuit. A signal taken out of a memory A to be measured by the probe is enhanced with the buffer, and is written on a memory B prepared on the extension slot of a universal small computer. It follows that the memory B prepared on the extension slot of the universal small computer is provided with the same content as that of the memory A. In such a way, the memory content can be read out independently in real time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a random memory monitor that can be suitably used for evaluation and analysis during prototype production of electronic circuits incorporating random memory, and for inspection and guarantee during mass production. This is what we are trying to provide.

[Conventional technology 1] When developing a system using a microprocessor, development must proceed while referring to the contents of the random memory built into the system. Conventionally, ICE (Inne
r Circuit Emulator). [Problems to be Solved by the Invention] Therefore, it is necessary to prepare a corresponding ICE for each different type of microprocessor.

When trying to monitor the contents of random memory in real time, it is necessary to use the internal memory of the ICE, which often has limitations such as capacity and speed. When developing a program, evaluation is carried out using ICE as described above, but most of this work involves checking the memory contents. Therefore, by making it possible to read memory contents independently in real time during program evaluation, many tasks can be completed. Furthermore, since the present invention can be applied to all circuits, it is possible to simplify the ICE function and reduce the cost. Therefore, this invention supports electronic circuit development and manufacturing at low cost. [Means for Solving the Problems] The random memory monitor of the present invention uses an external memory (high capacity, high speed) that is equivalent to or higher than the random memory to be monitored, on an electronic circuit using a microprocessor or the like. and means for always writing the same data as the random memory on the electronic circuit into the external memory,
This device is characterized by having a control circuit prepared outside the electronic circuit and a general-purpose small computer that reads out this data in real time. [Operation] That is, the signal taken out from the memory A to be measured by the probe is strengthened by the buffer and written to the memory B prepared on the expansion slot of the general-purpose small computer. A control circuit for switching between writing and reading is provided around this memory B.

Additionally, software for reading/displaying or storing/storing the memory contents is also prepared as necessary.

Memory B prepared on the expansion slot of a general-purpose small computer always has the same contents as the memory to be measured A since writing is prioritized.

[Embodiment] Next, an embodiment of the random memory monitor of the present invention will be described based on the drawings. In the figure, 1 is a probe for extracting a signal from a memory to be measured (not shown). The above measured memory is
It consists of random memory to be monitored on an electronic circuit such as a microprocessor. This probe 1 is connected via a buffer 2 to an external memory 5 (high capacity and high speed) that has a capacity equal to or higher than the random memory to be monitored. The buffer 2 and the clock 3 constitute a buffering section 13, which is connected to a write/read section 14 comprising a control circuit having the following configuration. That is, in the write/read unit 14, 4 is a buffer provided between the buffer 2 and the external memory 5, and is connected to the external memory 5 via a data bus 9 and an address bus 10. Also, 6 is a latching relay,
Each is connected to a bus between the data bus 9 and the output terminals of the OE of the external memory 5 and the encoder 25. Further, the buffer 7 is connected to the buffer 4 and the address bus 10 through NOT circuits 26, respectively. And between the NOT circuit 26 and the encoder 25
is connected to the input terminal of A latching relay 8 is connected to the bus 1l for applying a read pulse to the external memory 5 via an encoder 25 and to the buffer 4, and outputs a signal 12. Next, the operation of this invention will be explained.

Of the signals retrieved from the memory under measurement by probe 1,
Signals passing through the data line 2l and the address line 22 are buffered by the buffer 2. Other memory control signals 23 undergo timing changes at clock 3 for writing to and reading from external memory 5.

The signal 24 buffered in buffer 2 enters buffer 4. The buffer 4 is a 3-state buffer and outputs signals to the data bus 9 and address bus 10 only when writing to the external memory 5. When reading data from the external memory 5, the address bus 10 is occupied by writing a read address to the buffer 7, and each time a read pulse is applied to the bus 11, the memory contents are latched into the latch 6 through the data bus 9. Ru. Since the data bus 9 and the address bus 10 share write/read functions, they may conflict with each other. If a conflict occurs, writing takes priority. When writing occurs, output from buffer 4 is permitted, and output from buffer 7 is not permitted.

Also, ○E in external memory 5 is not permitted. If reading is being performed simultaneously at this time, the data written to the latch 6 will be incorrect data. For this reason, a latch 8 is provided, and if a write operation occurs during reading,
By checking the signal 12, it is recognized whether the data is normal or not.

The buffering section l3 between the buffer 2 and the clock 3 is
It is placed near probe 1 to reduce the influence on the circuit under test. The writing/reading section 14, which consists of the buffer 4 or the latch 8, is installed in an expansion slot of a general-purpose small computer, and the buffering section 13 and the writing/reading section i4 can be installed at a distance of 1 m or more.

4. [Effects of the Invention] The random memory monitor of the present invention can provide an inexpensive device that can instantly and easily read out memory contents without any influence on the circuit under test.

[Brief explanation of drawings]

The drawing is a block diagram showing an embodiment of the random memory monitor of the present invention. 1... Blob 2... Battufa 3...
Clock 4...Buffer 5...External memory 6...Latch 7...Buffer
8...Latch 9...Data path 10...
Address bus 11...Bus l2...Signal 13...Buffering section 14...Writing/reading section

Claims (1)

[Claims] 1. On electronic circuits using microprocessors, etc.
It is equipped with an external memory (high capacity, high speed) of the same or higher capacity as the random memory to be monitored, a means for always writing the same data as the random memory on the electronic circuit to the external memory, and an external memory of the electronic circuit. A random memory monitor characterized in that it has a control circuit prepared for the data, and a general-purpose small computer that reads this data in real time.