JPH05224989A - Microprocessor containing cache memory and its trace analyzer - Google Patents

Abstract

PURPOSE:To easily and accurately debug a program requiring the real time properties through a trace analyzer by changing the tracing way of a microprocessor in response to the mode display signal applied on the terminal of the analyzer. CONSTITUTION:A microprocessor 101 is provided together with a main memory 102, a trace analyzer 103, and a trace memory 104. These component elements are connected to an address bus, a data bus, and a status bus respectively. The microprocessor 101 supplies a mode display signal 105, an instruction execution start signal 106, a branch instruction producing signal 1.07, and an interruption branch producing signal 108 to the analyzer 103. The analyzer 103 reads a program stored in the memory 102 and acquires and holds a static execution flow of the program before the start of the debug. This execution flow consists of the address and the branching destination address of the memory 102 corresponding to a program counter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor having a cache memory and a trace analyzer for analyzing the operation history of the microprocessor.

[0002]

2. Description of the Related Art A microprocessor put into practical use in the early 1970s is an arithmetic unit that decodes instructions and executes arithmetic / control operations, and is realized on a silicon chip. With the subsequent development of LSI technology and the broadening and sophistication of market needs, the performance has been increasing, and today, a model having a word length of 32 bits has been commercialized. In addition to the essential components such as registers, arithmetic circuits, and control circuits, there are quite a few that have a cache memory built-in. As is well known, the cache memory is a high-speed small-capacity memory provided inside the central processing unit in order to satisfy the trade-off requirements of high speed and large capacity for the internal memory of the computer.

As described above, even in the case of a microprocessor, if the complexity is increased up to this point, debugging of them becomes a problem. Trace, trap, single step and the like are known as techniques for this kind of debugging, but trace is suitable for general debugging. As is well known, tracing is performed by providing a trace analyzer and a trace memory outside a central processing unit or a processor that executes a program to be debugged. The trace analyzer stores the addresses of the instructions executed by the microprocessor in the trace memory one by one, and later analyzes the stored contents to enable debugging.

However, unless special measures are taken, the memory access stays inside the microprocessor while the cache memory is operating, so the trace analyzer cannot directly detect the data required for the trace. Therefore, conventionally, the cache memory is usually invalidated for tracing.

However, in the case where the cache memory is invalidated, the operation of the microprocessor is largely different from that in the case where the cache memory is valid in terms of instruction execution clock, instruction execution timing, etc., and accurate debugging cannot be realized. There is a problem.

Therefore, in order to enable tracing while keeping the cache memory in an effective state, in the conventional microprocessor with a built-in cache memory, the execution start of an instruction, the generation of a branch instruction and the address of the branch destination are static. Each has a terminal for externally displaying whether or not it can be designated. In addition, the conventional trace analyzer holds an execution flow in which a program is statically analyzed in advance, and a signal that is supplied from each of the above-mentioned terminals is used as a clue to construct a dynamic instruction processing sequence based on the execution flow. Is becoming

By adopting the above configuration, the conventional microprocessor with a built-in cache memory can realize the trace when the cache memory is fixed in the invalid or valid state. However, for programs that dynamically enable or disable the cache memory, as in the field of robot control and games in which the introduction of microprocessors has become active in recent years, the method of analyzing the program execution state is dynamically changed. I have to switch.

For this reason, most of the conventional microprocessors with a built-in cache memory have a terminal for externally setting the validity or invalidity of the cache memory and the cache memory depending on the instruction execution result or the internal state of the microprocessor. An internal register capable of setting validation or invalidation is provided, and the validation of the cache memory is determined by the combined condition of both.

A conventional trace analyzer for analyzing the operation history of such a microprocessor reads out the above-mentioned internal register by software, and based on this value and a setting signal from the outside, whether the cache memory is valid or not. Requires hardware to determine.

[0010]

The conventional microprocessor and its trace analyzer described above require hardware for reading the internal register to determine whether the cache memory is enabled or not. This kind of hardware will become huge,
There is a problem in that the real-time property of the analysis of the operation history cannot be guaranteed, and thus it is not suitable for the trace of the program in the device that makes such real-time property a life. An object of the present invention is to provide a trace analyzer that immediately determines whether the cache memory is valid or invalid, and thereby easily realizes accurate debugging of a program that requires real-time processing.

[0011]

Means order to solve the problem cache memory-based microprocessor of the present invention includes a mode display terminal for displaying whether the cache memory is enabled to the outside. The signal at this terminal is guided by a mode detection mechanism which detects whether the cache memory is enabled. The mode detection mechanism is externally set via the cache memory enable terminal, and is set by the instruction execution result and the internal state of the microprocessor. Preferably, the microprocessor with a built-in cache memory according to the present invention, in addition to the above-mentioned components, further externally displays whether execution start of an instruction, occurrence of a branch, and whether or not a branch destination address can be statically determined. It has a terminal to do. Further, the trace analyzer of the present invention is characterized in that the trace method of the microprocessor is changed depending on whether or not the cache memory is valid. Preferably, the trace analyzer of the present invention holds an execution flow obtained by statically analyzing a program in advance, and when the cache memory is validated, execution start of an instruction from a microprocessor, branch occurrence, and branch destination A signal indicating whether or not an address can be statically determined is used as a clue to dynamically assemble and trace the instruction execution order based on the execution flow. In the case of a branch whose branch destination address cannot be statically determined, an interrupt is issued to the microprocessor. More preferably, the trace analyzer of the present invention stops tracing when cache memory is enabled.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first trace system of the present invention shown in FIG. 1 is a microprocessor 101 and a main memory 10.
2, trace analyzer 103 and trace memory 10
4, which are connected by an address bus, a data bus and a status bus. Further, a mode display signal 105, an instruction execution start signal 106, a branch instruction generation signal 107 and an interrupt branch generation signal 108 are supplied from the microprocessor 101 to the trace analyzer 103.

The microprocessor 201 shown in FIG.
Shows the details of the microprocessor 101 of FIG. 1, and has an instruction execution unit 202, a cache memory 203, an internal register 204, a mode detection mechanism 205, a cache validation terminal 206 and a mode display terminal 207.

The instruction execution start signal 106, the branch instruction generation signal 107 and the interrupt branch generation signal 108 shown in FIG.
The illustration is omitted in FIG. 2 in order to avoid complication of the drawing.

The main memory 102 stores a program to be debugged, and some data (instruction group) in the main memory 102 is stored in the cache memory 203 in a unit of a fixed area (block) having continuous addresses. Is loaded. When the instruction execution unit 202 makes a memory access in the enabled state of the cache memory 203, if a cache hit occurs, the cache memory 20
3. If there is a cache miss, the main memory 102 is accessed. Then, an instruction group including the instruction read from the main memory 102 at the time of a cache miss is loaded into the cache memory 203.

The instruction execution unit 202 executes the read instruction and, as a result, the internal register 204.
The cache memory 203 is set to enable or disable. However, the internal register 204 may be set to enable or disable the cache memory 203 according to another internal state of the microprocessor 202.

The output of the internal register 204 is guided to the mode detection mechanism 205. The mode detection mechanism 205 includes
An instruction to validate or invalidate the cache memory 203 from the outside, which is supplied from the cache activation terminal 206, is also input. The output of the mode detection mechanism 205 is guided to the cache memory 203 and the mode display terminal 207 and immediately displayed outside. The signal on the mode display terminal 207 is supplied to the trace analyzer 103 as a mode display signal 105 indicating whether or not the cache memory 203 is enabled. Trace analyzer 1
03 determines the tracing method in response to the mode display signal 105 and displays the execution history of the program in the trace memory 10.
Record in 4.

Prior to the start of debugging, the trace analyzer 103 reads and analyzes the program in the main memory 102 to obtain and retain a static execution flow of the program. This execution flow is specifically composed of the address of the main memory 102 corresponding to the value of the program counter and the branch destination address at the time of branch, but a dynamic branch instruction in which the branch destination address is determined by the result of instruction execution. It is not something that can be dealt with.

The operation of this embodiment will be described with reference to FIG. 3, which is a flow chart showing the trace operation of the trace analyzer 103 shown in FIG.

(1) When the cache memory is not valid When the microprocessor 101 executes an instruction according to a program, it outputs the address and status signal of the instruction to the address bus and the status signal, respectively, and the main memory 102 uses this address bus. The data (instruction) corresponding to the above address is output to the data bus. The microprocessor 101 reads the data on this data bus and executes the instruction.

In the trace analyzer 103, since the mode display signal 105 does not display the validity of the cache memory 203 (step 301 in FIG. 3), it is a bus cycle (step 302), and the status signal is an instruction fetch ( When the step 303) is detected, the address on the address bus is observed (step 304),
The instruction is traced by writing it in the trace memory 104 (step 305).

(2) When the cache memory is valid In this case, when a cache hit occurs, the microprocessor 101 does not access the main memory 102. Therefore, the trace analyzer 103 observes the bus to advance the instruction processing. Can not know the information that indicates. Further, even if the cache mishit occurs and the main memory 102 is accessed, the microprocessor 1
01 does not always immediately execute the instruction read from the main memory 102 to the data bus. Therefore, the trace analyzer 103 changes the instruction tracing method by properly using the built-in program counter, the previously-obtained execution flow, and the interrupt mechanism according to the type of instruction as follows.

(2.1) When the Instruction Does Not Branch The instruction execution unit 202 sequentially reads the cache memory 203 according to the value of the built-in program counter and executes the instructions. The address of the main memory 102 corresponding to the value of the program counter can be known from the execution flow obtained in advance. The value of this program counter is, of course, kept the same as the value of the program counter in the instruction execution unit 202.

In the trace analyzer 103, the mode display signal 105 and the instruction execution start signal 106 are true (step 3
06) and when it is detected that the branch instruction generation signal 107 is false (step 307), the program counter is incremented (step 308) and the address obtained as described above is written in the trace memory 104 (step 309). ) Can be used to trace instructions.

(2.2) When an instruction branches to an address that can be statically determined That an instruction can be statically determined means that it can be determined before its execution by program analysis. When the program branches to such an address, the processing progresses with a value far from the value of the program counter up to that point. Therefore, when the trace analyzer 103 detects that the interrupt branch occurrence signal 108 is false (step 31
0), the branch destination address in the previously obtained execution flow is transferred to the program counter (step 31).
1), write to the trace memory 104 (step 31)
By 2), the instruction can be traced.

(2.3) When an instruction branches to an address that cannot be statically determined In this case, the inside of the trace analyzer 103 is:
There is no data to trace. This is because the execution flow obtained in advance corresponds only to the static, that is, the branch instruction whose branch destination address is known in advance.

When the trace analyzer 103 detects that the interrupt branch occurrence signal 108 is true (step 3
10), microprocessor 10 with built-in interrupt mechanism
An interrupt is generated at 1 (step 313). Then, the value of the program counter in the microprocessor 101 is stored in its own program counter (step 3
14), write the corresponding address of the main memory 102 to the trace memory 104 (step 315)
This allows you to trace instructions. To understand this, when an interrupt branch occurs, the microprocessor 101
It should be recalled that the program counter of 1 has an interrupt destination address set.

It should be noted that each of the final steps 305, 309, 312 and 315 in the four cases described above have all returned to step 301, the beginning of the flowchart. That is, since it is again asked in step 301 whether or not the cache memory 102 is valid, there is a feature that the tracing method can be dynamically changed.

The second trace system of the present invention shown in FIG. 4 eliminates the instruction execution start signal 106, the branch instruction generation signal 107 and the interrupt branch generation signal 108 in the first trace system shown in FIG. It is composed.
As a result, the trace analyzer 403 will stop the trace when the validation of the cache memory is displayed. Because the trace analyzer 403
This is because the information necessary for tracing when the cache memory is enabled cannot be obtained.

Therefore, the trace analyzer 403 has a simpler structure, and the trace analyzer 10
3 does not require a program pre-analysis function and the like, and the flowchart of FIG. 3 also returns to step 301 if "Y" in step 301. Further, the block diagram of the microprocessor 401 is common to that shown in FIG.

In this embodiment, the operation when the cache memory is not activated is no different from the operation of the first embodiment.

When the cache memory is activated, the trace is stopped, and when it is not activated, the trace is restarted. That is, the trace analyzer 403 is simplified by interrupting the trace while the cache memory is valid.

Even if the trace is interrupted, the cause of the interrupt is clear, so that the debugging thereafter is relatively easy. Techniques such as the traps and single steps described above may be used for this.

[0034]

As described above, according to the present invention, it is possible to easily perform accurate debugging of a real-time program executed by the microprocessor with only a slight change in the microprocessor and the trace analyzer. ..

[Brief description of drawings]

FIG. 1 is a block diagram of a first trace system including a microprocessor with a cache memory and a trace analyzer according to a first embodiment of the present invention.

2 is a block diagram of the microprocessor shown in FIG. 1. FIG.

FIG. 3 is a flowchart illustrating an operation of the trace analyzer shown in FIG.

FIG. 4 is a block diagram of a second trace system including a microprocessor with a cache memory and a trace analyzer according to the second embodiment of the present invention.

[Explanation of symbols]

 101, 201, 401 Microprocessor 102, 402 Main memory 103, 403 Trace analyzer 104, 404 Trace memory 202 Instruction execution unit 203 Cache memory 204 Internal register 205 Mode detection mechanism 206 Cache activation terminal 207 Mode display terminal

Claims (6)

[Claims] 1. An internal register for enabling or disabling a built-in cache memory according to an instruction execution result or an internal state, and whether or not the cache memory is enabled by a content held in the internal register. A cache memory built-in microprocessor having a mode detecting mechanism for detecting and a mode display terminal for displaying an output of the mode detecting mechanism to the outside. 2. The cache memory built-in type according to claim 1, further comprising a cache validation terminal for externally instructing the mode detection mechanism to validate or invalidate the cache memory. Microprocessor. 3. The cache according to claim 1, further comprising a plurality of terminals for externally displaying whether instruction execution start, branch occurrence, and whether or not a branch destination address can be statically determined. Microprocessor with built-in memory. 4. The trace analyzer for a microprocessor according to claim 1, wherein the trace method of the microprocessor is changed in response to a signal on the mode display terminal. 5. An execution flow obtained by statically analyzing a program in advance, and a mechanism for generating an interrupt when the branch destination address cannot be statically determined, and a signal on the mode display terminal is When the activation of the cache memory is displayed, the execution of the instruction is started, the occurrence of the branch and the indication of whether or not the branch destination address can be statically determined based on the execution flow or by the interrupt mechanism. 5. A trace analyzer as claimed in claim 4 for a microprocessor as claimed in claim 3 wherein the order is dynamically assembled to provide traces of the microprocessor. 6. The trace of the microprocessor is stopped when the signal on the mode display terminal indicates the activation of the cache memory.
Trace analyzer according to claim 4, for the described microprocessor.