JPS59147565A - Method for converting magnification of picture - Google Patents

Abstract

PURPOSE:To attain the magnification converting processing, to make the hardware constitution easy and to attain high speed processing by dividing a picture so as to increase or decrease the number of picture elements by 1 when the magnification conversion is processed. CONSTITUTION:The dividing picture element number from a data input section 100 is set respectively to sub and main scanning direction control circuits 102, 103 through signal lines 107, 108 in synchronizing with a clock signal of a picture data transfer control circuit 101 respectively. The circuit 101 outputs a picture transfer request signal 112 by the number of picture elements in a picture except at the picture element insertion and removal in main and sub scanning directions, and a picture data transfer circuit 104 transfer the picture data for one picture element's share corresponding to a signal 112. The circuits 102, 103 transfer respectively control signals 113, 114 to sub and main scanning direction magnification converting circuits 105, 106, insert and eliminate the picture element of one line at the insertion and elimination of picture element, allowing to perform the sub and main direction magnification converting processing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image processing device, and more particularly to a magnification conversion method that allows a digital image to be scaled to an arbitrary magnification.

Some facsimile IJ devices have a linear density conversion function; for example, these devices have the function of transmitting an 84th edition (2) original and outputting it on A4 size paper), but here we will convert the 34th edition. The magnification has been converted to the 4th edition.

The magnification conversion processing method of this apparatus changes the magnification of an optical system that reads image density information from a document depending on the size of the document to be transmitted.

In this case, there is a drawback that the optical system is complicated, which hinders cost reduction and miniaturization of the device.

In image processing devices such as word processors that have character generator patterns as memory and display or record them, the size of the character butter// has usually been limited, but when creating a document, 1! There was a demand to use fonts of various sizes.

This can be done by storing character generator patterns of various sizes in memory, but this method has the disadvantage of requiring an enormous amount of memory.

In order to improve the above-mentioned drawbacks, various methods have been proposed in which character generator patterns of one (3) size are stored in the memory and the size of the pattern is converted electrically.

Among the methods proposed in the past, there are methods that divide the image t and convert the magnification. (Benjo, et al.: 6 kanji butter/enlargement/reduction method”, IEICE Image Engineering Study Group Materials, 7)
9-1, P1-F10, (1979)).

In this method, (1) the size of the pattern to be stored in the memory is an image of 56 x 56 pixels;

(2) When converting the magnification, the image is divided into units arranged in a matrix of 2×2 or 3×3 strokes.

(3) The magnification is a limited magnification based on % times or % times.

(4) The device stores the pattern of the divided image and the pattern obtained by converting the magnification of the divided image as a pair in the memory, searches for which pattern the divided image belongs to in the magnification conversion process, and calculates the paired image (4). A process is performed in which the pattern is replaced with a rate-converted pattern.

The above method cannot be applied to images of arbitrary size because (1) the size of the image is determined;

(2) Since the magnification is limited, it cannot be applied to conversion at any magnification.

(3) It is necessary to divide the image into a matrix and search which pattern the divided image belongs to, which complicates the processing and impedes speeding up of the processing.

There are the above drawbacks.

The present invention eliminates the drawbacks of the above-mentioned conventional example, and enables high-speed magnification conversion processing of an image of any size at any magnification.

FIG. 1 illustrates the principle of the invention. 1 is an image, 2 is an image that is twice enlarged from image 1, 3 and 4 are images that are obtained by dividing image 1 into two, and 5 and 6 are images that are obtained by enlarging divided images 3 and 4 by 2 times, respectively. .

(5) The principle of the present invention will be explained below with reference to FIG.

Image 2, which is an enlarged image of image 1, can also be obtained by enlarging images 3 and 4 obtained by dividing image 1, respectively, and combining the enlarged images 5 and 6. From Figure 1, in general,
By arbitrarily dividing the image, converting the magnification of each divided image, and then composing the magnified images,
It can be seen that there is a characteristic that an image can be obtained by converting the magnification of the original image. The present invention makes the most efficient use of this feature.

FIG. 2 shows the principle on which the invention was discovered. 11 is a digital image obtained by extracting one line from the digital image, 1
2 to 17 are each pixel in the image iii, 18 is an analog image obtained by enlarging the image 11, 19 is a digital image obtained by digitizing the image 18, and 20 to 27 are each pixel in the image 19.

Magnification conversion of a digital image will be explained using FIG. In magnification conversion of a digital image, the image to be converted and the converted fc image are both gauge (6) and the converted image.

The image 18 is an analog image obtained by photographically enlarging the digital image 11. When it is desired to digitally enlarge the image 11, a digital image 19 can be obtained by performing sampling and quantization processing on the analog image 18. However, photographic enlargement processing, sampling processing, and quantization processing are complicated when carried out. This is done using a computational process.

However, we have discovered that there is an extremely simple rule to follow if a digital image is divided and the divided image is converted and the number increases or decreases by one pixel.

FIG. 6 shows the relationship between images. 50 is a divided image, and 31 is an enlarged image of the divided image 60.

The relationship between images will be explained below. - The number of pixels in @31 is one more than the number of pixels in image 30. f1 to f3 in Figure 3
and t1 to t4 indicate the amplitude value of each pixel. In the figure, the value of the first pixel of image 31 is determined by the values of the (1-1)th and first pixels, and in the case of a binary image, f1 to f5
and f, ~f4(7) The following relationship holds true.

t, :D(fl) ==41(1) 2 1□: D C-f1+-r2) = f 2
(2) 6 1 t, = D (-f2+-f, ) = f2(3
)3 242p(f,)=r, (4) Here, D is a quantization operator, for example, D(x)==1; when 1≧x′2−
(5) 2 :=O; -> When X≧0 (6) (1)
From equation (4), image 51 can be created by inserting one pixel between the first and second pixels of image 300, or between the 28th and third pixels, and making the amplitude value equal to the amplitude value of the second pixel.

In the above, there is a condition that the number of divided pixels is increased or decreased by one pixel by the magnification conversion process, but as explained earlier, there is no restriction on the position of division (8), so the enlargement process The insertion point of one pixel in the case of , and the removal point of one pixel in the reduction processing can be specified appropriately before the processing.

The amplitude value of the pixel to be inserted may be determined based on the amplitude value of the pixel adjacent to the insertion position. For example, let the amplitude value be (1) the amplitude value of one of the adjacent pixels (2)
It is conceivable to use the logical sum of the amplitude values of two adjacent pixels.

FIG. 4 shows an example of enlargement processing.

The conditional expression for increasing or decreasing the number of divided pixels by one pixel by magnification conversion processing is as follows.

(1) 2') When m > 1, or (9) Or, where m is the number of divided pixels, and A is the magnification [x], whichever is the largest integer not exceeding X (7) to (1D) is adopted. You can specify as appropriate.

The above explanation has been given for one dimension, but in the case of two dimensions, the same procedure can be performed in each direction. Also, the magnification is 2
When the magnification is larger than the magnification, or when the magnification is smaller than the magnification, this can be achieved by, for example, repeating the magnification conversion process. 100 is a data input section, and 100a is a signal specifying the number of pixels of an image. The data input section 100 is connected to the main running blue direction (
It consists of a panel switch that sets each magnification and the number of pixels in the horizontal (horizontal) and sub-scanning directions (vertical), an arithmetic circuit that calculates the number of divided pixels from the magnification, and a circuit that transmits each value to each control circuit. The image data (10) is transferred by the signal 100a, and the magnification of an image of any size is converted by changing the set value (number of pixels of the image) of the counter 121 that counts the cumulative number of 10 in the transfer control circuit 101 to a desired value. is also possible.

In FIG. 5, 101 is an image data transfer control circuit;
2 is a sub-scanning direction control circuit, 103 is a main-scanning direction control circuit, 104 is an image data transfer circuit, 105 is a sub-scanning direction magnification conversion circuit, 106 is a main-scanning direction magnification conversion circuit, 107
108 is a signal line for externally setting the number of divided pixels in the sub-scanning direction; 109 is a signal line for informing when to insert or remove a pixel in the sub-scanning direction; 110 111 is a signal line for transmitting pixel insertion or removal in the main scanning direction; 111 is a clock signal line; 112 is a signal line for controlling image data transfer;
5 is a signal line that controls the circuit 105, 114 is a circuit 106
Signal lines 115 to 117 control the image data, and signal lines 115 to 117 transfer image data.

The operation will be explained below.

In this embodiment, the image data transfer control circuit 101 operates in synchronization with a clock signal generated in (11). First, the data input section 100 sets the number of divided pixels obtained using formulas (7) to (10) to the sub-scan direction control circuit 102 and the main scan direction control circuit 106 through signal lines 107 and 108. Image data transfer control circuit Reference numeral 101 issues an image data transfer request signal for only pixels in an image, except when pixels are inserted or removed in the main scanning direction and sub-scanning direction.An image data transfer circuit 104 stores image data in memory or scans the image. Accordingly, image data for one pixel is transferred in response to the image data transfer request signal in the order shown in FIG. Pixels in the scanning direction (
A control signal 113 is transferred to the sub-scanning direction magnification conversion circuit 105 after checking whether it is inserted or removed (one line pixel).

The sub-scanning direction magnification conversion circuit 105 inserts or removes one line of pixels at the time of pixel insertion or removal, that is, performs a sub-scanning direction magnification conversion process in accordance with the control signal 116. The main scanning direction control circuit 103 (12) manages pixel insertion or removal in the main scanning direction, and sends a control signal 114 to the main scanning direction magnification conversion circuit 106.
Transfer. The main scanning direction magnification conversion circuit 106 inserts or removes one pixel at the time of pixel insertion or removal, that is, performs magnification conversion processing in the main scanning direction in accordance with the control signal 114.

In the embodiment described above, the order of the sub-scanning direction magnification conversion process and the main scanning direction magnification conversion process may be reversed.

Next, the above-mentioned image data transfer control circuit will be further explained with reference to FIG.

FIG. 7 shows one embodiment of the image data transfer control circuit. 1
20 is a clock pulse generator, 121 is a counter, 1
22 is a gate circuit, 123 to 124 are inverters, 12
5 is a three-input AND gate.

The operation will be explained below.

Clock pulse generator 120 constantly generates a clock pulse signal during operation of the system. 109 and (13), the number of pulses of the clock pulse signal is counted while the control signals 109 and 110 are not coming, and the gate circuit 122 is opened until the value becomes equal to the number of pixels in the image, and the image data is A transfer request signal 112 is issued. One pulse of the image data transfer request signal 112 requests the image data transfer circuit 104 to transfer data for one pixel.

Next, the sub-scanning direction control circuit 102 shown in FIG. 5 will be explained in detail.

FIG. 8 shows one embodiment of the sub-scanning direction control circuit 102.

130 is an inverter, 151 is an AND gate, 162 is a clock pulse counter, 133 is a Hall line counter, 154 is a comparator, 135 is an inverter, 136
137-138 are signals inside the circuit, 169 and 141 are sub-scanning direction control circuit 10
5, which is the signal that controls O.
41 is a timing chart. The operation will be explained below.

(14) The clock pulse signal 111 is the source of the synchronization signal of this system. The signal 139, which is the logical product of the signal 111 and the control signal 110 from the main scanning direction control circuit, is obtained by removing the pulse signal at the time of the control signal 110 from the signal 111, and serves as a synchronization signal for operating the sub-scanning direction magnification conversion circuit. Become.

Signal 139 is also synchronized with pixel data transfer signal 115. The counter 132 counts the number of pulses of the signal 139, that is, the number of transferred pixels, and when it becomes equal to the number of pixels in one scanning line, t! Outputs 1 pulse.

That is, the signal 137 is a pulse signal synchronized at the start of scanning of each line. A line counter 133 counts the scan lines of transferred pixels. L1 to comparator 164
The number of pixels, ie, the number of scanning lines, of the divided images in the sub-scanning direction is set from the outside.

When the value set now is m, the line counter 153
If the value of is m, a signal 109 is output.

Signals 109 and 140 are pixels (lines) in the sub-scanning direction
At the same time as controlling the insertion time, the value of the line counter 133 is cleared. D-clip flow (15) The tube outputs a signal 141 which is the signal 140 delayed by the time of one scanning line. The sub-scanning direction magnification conversion circuit operates using signals 139 and 141 as control signals.

Next, the sub-scanning direction magnification conversion circuit shown in FIG. 5 will be further explained.

FIG. 10 shows one embodiment of a sub-scanning direction magnification conversion circuit.

151 to 153 are shift registers equal to the number of pixels for one line, 154 is an OR gate, 155 to 156 are AND gates, 157 is an inverter, 158 is an OR gate, 159 is a signal selection circuit, 161 to 165 are circuits It is a signal within.

FIG. 11 is a timing chart of each signal. The operation will be explained below.

Image data signals 115 are transferred from the image data transfer circuit 104 in the order shown in FIG. The shaded area in the figure is a period during which no image data is transferred in response to the control signal 109, as described above.

After passing through the shift register 151, the signal 161 is input to a second signal select circuit 159. Also signal 161 (16
) is input to the shift register 152 and the OR gate 154, becomes a signal 163, passes through the shift register 153, becomes a signal 164, and is input to the signal select circuit 159. The signal selection circuit 159 selects the signal 161 and the signal 164 based on the cocoon weight control signal 141 and outputs the signal 165. In this embodiment, since pixels for one line are inserted every m lines, a magnification conversion of (m+1), z, is performed in the sub-scanning direction.

Since the value of m is given from the input section 100, it goes without saying that it is variable.

In the above embodiment, the logical sum of 1m-1 and 4m is taken as the lkO value, but the invention is not limited to this.

Next, the main scanning direction control circuit shown in FIG. 5 will be further explained.

FIG. 12 shows one embodiment of the main scanning direction control circuit. 17
0 is a counter, 171 is a comparator, 172 is an inverter, 173 is a shift register, 174 is an AND gate, and 175 to 178 are signals.

Figure 13 is a timing chart of each signal (17) Ru. The operation will be explained below.

First, the number of divided pixels (n) in the main scanning direction is set from the outside to the comparator 171 through the signal line 108. The clock pulse signal 111 is counted by a counter 170, and its value is compared with the value set in a comparator 171. When both are equal, a signal 110 is output. Signal 110 is a signal for controlling image data transfer control circuit 101 and sub-scanning direction control circuit. Signal 176 clears counter 170 while AND gate 1
74 and input to the D flip-flop. The signal 176 input to the D flip-flop is the signal 17 delayed by one clock.
Multiple outputs such as 8 are output. Signal 111 is a system synchronization signal,
Signal 177 is a pixel insertion or removal control signal, signal 17
8 is input as a signal selection control signal to the main scanning direction magnification conversion circuit.

Next, the main scanning direction magnification conversion circuit will be described in detail.

FIG. 14 shows one embodiment of the main scanning direction magnification conversion circuit.

180 is a D flip-flop, 181 (18) is an OR gate, 182 is a signal select circuit, 183 is a D flip-flop, and 184 to 186 are signals.

FIG. 15 is a timing chart of each signal. The operation will be explained below.

Signals 116 are input in the order shown in FIG. In the shaded area in the figure, j5 afi is held by the control signal 110 sent to the sub-scanning direction control circuit 102, and has a period twice as long as other signals. Signal 116 is input to the D71J block flop, becomes signal 184, and is input to signal select circuit 182 and OR gate 181.

The OR gate 181 performs the OR of the signal 116 and the signal 184 to obtain a signal 185. Signal selection circuit 186
Then, based on the control signal 178, the signal 184 and the signal 18 are
5 is selected and a signal 186 is issued.

The above signal relationship is as shown in FIG. In this example,
Signal 186 is one more stage D7 flip-flop 185
and becomes an output signal 117. (The D flip-flop 183 is used for signal shaping.) In this embodiment, an-
Although a signal having an amplitude value (19) that is a logical sum signal of 1 and 2In is inserted, the present invention is not limited to this.

As is clear from the above description, according to the present embodiment, one pixel is inserted for every On pixel in the main scanning direction, and enlarged by n+1/n times. n is given from the outside, and arbitrary magnification conversion is possible.

Although the above embodiment describes enlargement processing, the present invention is not limited to enlargement processing. The reduction process can be realized by providing a circuit for fine processing in each magnification conversion circuit, and performing a process of removing one line or one pixel in the circuit.

When selecting and using enlargement and reduction, the magnification conversion circuit is provided with an enlargement processing circuit and a reduction processing circuit, and the control circuit is provided with a circuit that instructs enlargement processing or reduction processing,
This can be achieved by using the sales output signal as an enlargement or reduction selection signal.

As explained above, when the magnification conversion process is performed, the number of pixels is 1.
By dividing the image (20) so as to increase or decrease the number of pixels, magnification conversion processing can be performed by inserting or removing one pixel during processing. This has the effect of simplifying the hardware configuration and enabling high-speed processing.

In the enlargement process, the amplitude value of the inserted pixel depends only on the amplitude value of the adjacent pixel in the direction in which the insertion point is enlarged, and does not depend on other pixels, which facilitates the process. It also has the effect of sequential processing.

Since digital images of any size can be processed sequentially, they can be easily used in digital printers such as facsimiles and digital displays such as liquid crystals.

[Brief explanation of drawings]

1 and 2 are diagrams showing the principle of the present invention, FIG. 5 is a diagram showing the relationship between images, FIG. 4 is a diagram showing one embodiment of enlargement processing, and FIG. 5 is a diagram showing an embodiment of the present invention. 6 is a diagram showing the transfer order of image data, FIG. 7 is a diagram showing one embodiment of the image data transfer control circuit, FIG. 8 is a diagram showing one embodiment of the sub-scanning direction control circuit, Fig. 9 is a timing chart of the 6th signal (21) shown in Fig. 8, Fig. 10 is a diagram showing one embodiment of the sub-scanning direction magnification conversion circuit, and Fig. 11 is a timing chart of each signal shown in Fig. 10. 12 is a diagram showing one embodiment of the main scanning direction control circuit, FIG. 13 is a timing chart of each signal shown in FIG. 12, and FIG. 14 is a diagram showing one embodiment of the main scanning direction magnification conversion circuit. 15 is a timing chart of each signal shown in FIG. 14. 101... Image data transfer control circuit 102... Sub-scanning direction control circuit 103... Main scanning direction control circuit 104... Image data transfer circuit 105... Sub-scanning direction magnification conversion circuit 106... Main Scanning direction magnification conversion circuit Applicant Canon Co., Ltd. (22) Tori Z diagram ΔR to Enkuniba blade, idan411IIl-1Il:Ikaki~177

Claims (1)

[Claims] (1) The image magnification conversion process is performed by arbitrarily dividing the image, performing magnification conversion processing on each divided image, and composing the converted images. How to convert the magnification of an image. (2. In claim 1, the magnification is (1,
When performing enlargement processing that falls within the range of 2) or reduction processing that falls within the range of (3A, 1), the number of pixels in the one-dimensional direction of the converted image is reduced by enlarging or reducing the divided image. An image magnification conversion method characterized by dividing an image into pixels in which the number of pixels increases or decreases by one pixel. (3) In claim 2, when the magnification is m, the number of pixels in the one-dimensional direction of the divided image m is (1) where (X) satisfies the largest integer that does not exceed X. An image magnification conversion method characterized by: (4) In claim 2, the image magnification is characterized in that when enlarging or reducing a divided image, one pixel is inserted into or one pixel is removed from the processed image. Conversion method. (5) An image magnification conversion method as set forth in claim 4, characterized in that, when performing enlargement processing or reduction processing, a position where one pixel is to be inserted or removed is appropriately designated prior to processing.