JPH0789644B2 - Image data scaling processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scaling device for image data used in digital copiers, facsimiles, other image processing devices, and the like.

2. Related Art FIG. 8 shows an external view of a conventional image reading apparatus. This image reading device has a shape like a top of a copying machine. A document is placed on the contact glass 2 and pressed by the document pressure plate 3. The operation unit 4 includes
It is equipped with several kinds of keys such as a reading start button and a density selection key, and several kinds of displays for displaying the setting status and the operating status, so that various functions can be set.

Start scanning by pressing the start button,
An image signal can be obtained.

9 and 10 show a typical configuration of the image reading apparatus shown in FIG. 8, particularly a reading optical system. FIG. 9 shows an optical system when a contact image sensor is used.
Figure 10 shows the optical system when a reduced image sensor is used. Other than this, there is a document whose document is moved and the optical system is fixed.

When the contact image sensor as shown in FIG. 9 is used, the optical system is a 1 × optical system. The original surface on the contact glass 2 is illuminated by the fluorescent lamp 5 and its reflected light 8
Enters the image sensor 7 through the self-hook lens 6. The image sensor 7 has a width equal to or larger than the document width (the depth direction in FIG. 9, that is, the main scanning direction X), and the image data of one line in the width direction is read at one time.

Number of lines sampled and sampling pitch Px
Depends on the number of pixels of the image sensor. After reading one line of data, the carriage 9 that integrates the fluorescent lamp 5, the self-hoc lens 6, and the image sensor 7 is driven in the direction of the arrow (sub-scanning direction Y), and the next line is read. There is also a mode in which the carriage 9 is continuously driven in the sub-scanning direction Y. The pitch Py between the lines is determined by the speed of the carriage 9, the charge storage time of the sensor 7, etc., but is normally set to the same sampling pitch Py as described above.

When a reduction type image sensor is used as shown in FIG. 10, the lens 14 reduces the original width of the optical image so as to match the size of the image sensor. In FIG. 10, three mirrors are used, but two or five mirrors are also conceivable. Reading in the main scanning direction X is the same as when using a contact sensor. In the sub-scanning direction Y, a first carriage that integrates the fluorescent lamp 10 and the first mirror 11 and a second carriage that integrates the mirrors 12 and 13 are independently provided from the original on the contact glass plate 2. It is driven so that the optical path length to the lens 14 is constant.

Here, in the conventional variable magnification method, with respect to the main scanning direction X,
This is performed by changing the optical path length of the optical system to change the reduction ratio, and in the sub-scanning direction Y, the speed of the moving body is changed. However, this method
It cannot be used when the contact type sensor as shown in the figure is used.

Even in the case of the compact sensor shown in FIG. 10, the lens
The range of the magnification change is structurally limited, such as the amount of movement that changes the positions of the 14 and the sensor 7 is large, but the magnification ratio does not change so much. However, a precise mechanism has to be used, and a coarse mechanism has a big problem that the read image is deformed.

In consideration of these conventional problems, recently, instead of optical scaling, image processing to obtain scaled image data by predictively calculating the scaled data from the same-magnification read data, so-called electrical scaling is used. I'm starting to be seen.

However, the electrical scaling currently proposed has a problem in the precision of the scaling, and if the scaling is performed accurately, the hardware becomes complicated and so-called zoom scaling such as 1% step,
There was a problem that it was difficult to deal with a wide range of magnifications.

Such a problem is that the data clock DCLK indicating the pixel unit division of the original image data is counted, the count value is set as the position i of the scaled image data, and one pulse of DCLK is generated.
That is, every time i increases by 1, 100i / specified scaling ratio R%
= Ji + Ri, an integer Ji and a decimal fraction Ri are calculated, the image data at the position x = Ji of the original image data and the image data adjacent thereto are sampled, and the sampled original image data and the scaled image data are obtained by the decimal fraction Ri. Calculate this and DCLK
This is improved by defining the scaled image data at the i-th position of the unit. That is, according to this, the scaled image data is obtained in synchronization with the data clock DCLK of the original image data, and the scaled image data is printed, transferred or transmitted by raster scanning synchronized with the reading or transfer of the original image data. It can be processed. Moreover, the scaling factor R can be set in fine 1% units, and the range of R can be set wide.

With this method, every time one pulse of the data clock DCLK of the original image data is generated, that is, every time the original image data is shifted by one pixel, the sampling position x =
Since Ji and the deviation Ri between the scaled image data position i and the position x are calculated, if the number of digits of Ri is large, the frequency of the data clock DCLK is limited by this calculation time. That is, one cycle of the data clock DCLK must be sufficiently longer than the sum of the time for executing these calculations and the time for calculating the sampled original image data and the time for calculating the scaled image data based on Ri. The cycle of the data clock DCLK depends on the image reading speed.
Is to reduce the image reading speed,
In addition, the speed of recording, transferring, transmitting, etc. of the scaled image data is also reduced. In addition, the large number of digits of Ri means that the number of signal bits required for Ri processing is large, which complicates the configuration of the signal line and the arithmetic processing hardware.

Object The present invention is capable of performing high-precision, fine, and wide-range zooming in real time, and an object thereof is to simplify the configuration of an arithmetic means for zooming.

First, the basic idea of the scaling executed by the scaling processor of the present invention will be described.

For example, in the image data obtained by the image reading apparatus shown in FIG. 9 or FIG. 10 (hereinafter referred to as original image data), the number of pixels in the main scanning direction X is N, and the number of pixels in the sub scanning direction Y is M.
Then, the distribution of the image data corresponding to the original image can be considered as shown in FIG. R% in the main scanning direction in Fig. 11
[N × R / 100] new data (hereinafter referred to as scaled image data) can be generated by scaling at a magnification of.

Here, two typical scaling algorithms will be described. Here, since the electrical scaling is performed only in the main scanning direction, the following description also applies.

First, in any method, it is necessary to recognize the position of the new sampling point 0 after scaling and obtain the original image data of the old sampling points of several pixels around the new sampling point 0 and their distances.

As shown in FIG. 12, the new sampling point 0 is between Sij and Sij ₊₁ of the original image data, and the distance between them is 0 .
Let r ₁ and r ₂ , and let P be the sampling pitch of the original image data.

A method for distributing the density level according to the distance between adjacent pixels adjacent interpixel distance linear Allocation 0 and the original image data. Scaled image data 0ik in Fig. 12
It _{is, 0ik = (1-r 1} / P) Sij + (1-r 2 / P) Sij +1 ... (1) obtained from.

Cubic function convolution method Interpolation calculation is performed using an interpolation function h (γ) as shown in FIG.

h (γ) is approximated by the following equation to γ that has been qualified with the sampling pitch P.

1-2 | γ | ² + | γ | ³ 0 <| γ | ≦ 1 h (γ) = 4-8 | γ | ² +5 | γ | ² − | γ | ³ 1 ≦ | γ | ≦ 2 0 2 ≦ | γ | (2) Using this h (γ), the scaled image data 0ij is 0ik = [h (1 + r ₁ / P) Sij ₋₁ + h (r ₁ / P) Sij + h (r ₂ / P _{) Sij +1 + h (1 +} r 2 / P) Sij +2 ] / _{[h (1 + r 1 / P} ) + h (r 1 / P) + h (r 2 / P) + h (1 + r 2 / P) ] ... (3 In addition to the above, there are methods such as the proximity pixel distance inverse proportion method and the proximity pixel area allocation method, but since they are relatively similar, the above is considered as a representative example.

All of these methods have been known for a relatively long time, and have been put to practical use mainly in the field of computer image processing.

For computer image processing, etc., when image data is stored in a high-capacity memory such as a page memory and then scaling processing is performed, these methods can be easily used, but there is no page memory and dedicated hardware is used. To do these things,
There are various restrictions.

When performing scaling with a digital copier, facsimile, etc. during scanning, it is necessary to perform raster scanning (line units) on the data input in raster scanning (line units) even after scaling processing, and also use the data clock ( Pixel sync pulse) needs to be constant at any magnification.

In other words, the data after the scaling process must be in the same format and at the same speed as the optical scaling. That is, real-time processing is required.

This means that if the digital copier system or the entire facsimile system can be scaled,
Different.

For example, if the printing speed of the printer can be changed during zooming, the data clock after zooming can also be changed. Further, in a system that performs transmission, it does not need to be raster scan data after scaling.

However, when the magnification is considered as a reading device or when the magnification processing is independently performed, the raster scanning processing is limited as described above.

The present invention provides a variable power device applicable to a reading device subject to these restrictions.

FIG. 6 and FIG. 7 are examples of time charts of pre-scaling data and post-scaling data that satisfy this restriction. In these, LSYNC is a horizontal cycle signal (line synchronization pulse: sub-scanning synchronization pulse) and reads image data of one line in the main scanning direction during one cycle of this signal. DCLK is a data clock (pixel synchronization pulse). At the timing shown in FIG. 6, it is assumed that pre-scaling data (pixel unit) Y is input to the scaling processing section from Si ₀ to Si _N in synchronization with DCLK within the period of LSYNC.

As a result, the scaled data Z is output. The output may be delayed from the data Y, but it must be synchronized with DCLK. The delay time (t ₂ −t ₁ ) is not particularly limited, but it should not change between lines, and t ₂ and t ₁ should always be constant.

In addition, when inputting / outputting data in line units,
As shown in the figure, the line buffer memory RAM1, RAM2 read data (input) may be delayed from write data (output).

Anyway, the most important and most difficult thing is to synchronize the scaled image data to DCLK at any magnification.

This requirement is relatively easy to achieve if the magnification is changed with several fixed magnifications, but especially in recent copying systems, a wide range of magnification and a small magnification of about 1%, which is called zoom magnification, are used. It is required to change the magnification all the time, and it has become necessary for digital copiers and facsimiles to meet these demands. Therefore, it is difficult to satisfy the demands of the preceding requirements in actually applying the above-described scaling method.

Configuration Therefore, in the scaling processing apparatus of the present invention, 100i / [specified magnification R (%)] = Ji + Ri, i is an integer, 0 ≦ Ri <
1, Ji is an integer, the integer Ji and the fractional Ri are calculated, and the data that represents the fractional Ri with the power of 2 as the denominator
First computing means for computing Bi; i is changed one by one in synchronization with a data clock defining a pixel unit of original image data, and if R <100, Ji
When -Ji _-1 = 2, the sampling designated position x of the original image data is designated to be a number larger by 2 and when Ji-Ji _-1 = 1 is designated to the designated position x is designated to be a number larger by 1; -Ji _-1 = 1 and the sampling position designating means for designating the position x to be a number larger by 1 and Ji-Ji _-1 = 0 to the position x as it is; counting the data clock to count the designated position x Sampling means for extracting the original image data and one or more image data adjacent thereto, and the original image data at the designated position x and the one or more original image data adjacent thereto in bit units in synchronization with the data clock. Second arithmetic means configured to use the bit shift so as to arithmetically operate the scaled image data by inputting the plurality of original image data with a coefficient whose denominator is a power of 2 corresponding to the data Bi. And

[Action]

According to this, the sampling position x of the original image data is designated by the first computing means and the sampling position designating means at a pitch corresponding to the scaling factor R, and the sampling means determines the sampling position x and the position adjacent to it. The original image data is extracted, and the second calculation means calculates the scaled image data by a predetermined logic, for example, the above processing. The sampling position designating means, the sampling means, and the second computing means are all data clocks of the original image data.
Since it operates in synchronization with DCLK, the scaled image data is in synchronization with the data clock DCLK. That is, variable-magnification image data can be obtained by real-time processing. Therefore,
It is possible to process the scaled image data in a raster scan type.

In addition, the data Bi that represents the decimal fraction Ri in the area division with the power of 2 as the denominator is calculated, and the scaling is performed using the original image data at the position x, one or more of the adjacent original image data, and the data Bi. Set the image data. By using the data Bi, for example, the values of the first and second terms on the right side of the equation (1) or the respective terms on the right side of the equation (3) can be automatically obtained. In this case, in the variable-magnification image data calculation, it is only necessary to add the values obtained in this way, division and multiplication are omitted, the number of calculation bits is reduced, and the calculation speed is increased. That is, the hardware configuration is simplified and the calculation speed is improved.

The first calculation means may calculate Ji and Ri by increasing i by 1 each time one pulse of the data clock DCLK appears, or i = 0 to R before the actual image reading.
−1, Ji and Ri are calculated in advance, these data are stored in a memory such as RAM3, and i is sequentially changed to a number larger by 1 in synchronization with the data clock DCLK. Then, Ji and Ri associated with the number may be read. In any case, Ji and
Ri will be sequentially specified in synchronization with the data clock DCLK.

As described above, the first calculation means 100i / [specified magnification R
(%)] = Ji + Ri, i is an integer, 0 ≦ Ri <1, Ji is an integer, an integer Ji and a decimal number Ri, the maximum integer Ji is calculated, and this Ji and the integer Ji calculated previously are calculated. Since the sampling position x (that is, Ji) of the original image data is specified by the sampling position specifying means based on Ji _-1 , the scaling factor R (%) is set to an arbitrary number and range with 1 as the minimum unit. Can be set. That is, zoom magnification in units of 1% is realized, and the zoomable range can be set extremely wide. In the embodiment of the present invention described later, the scaling factor is 1%.
As a unit, R = 50% to 400% is settable range.

In one embodiment of the present invention, memory means for storing original image data for one line; means for alternately setting the memory means for writing / reading; address counting means for giving write / read position x to the memory means; Prepare That is, a line buffer memory is provided.

The sampling position designating means, when writing to the memory means, provides the address counting means with a data clock DCLK that defines the pixel unit of the original image data as a count pulse, and when reading from the memory means, the data clock DCLK. I is increased by 1 for each pulse of, and when R <100, when Ji−Ji ₋₁ = 2, the count pulse 2DCLK having twice the frequency of the data clock DCLK is
When i−Ji ₋₁ = 1, the data clock DCLK is given to the address counting means as a count pulse, and when R ≧ 100, the data clock DCLK is given to Ji−Ji ₋₁ = 1 to the address counting means. _{When -1} = 0, the count pulse to the address counting means is cut off and the read position x of the original image data is designated. Prior to reading the original image, the calculation means 100i / [specified magnification R (%)] = Ji + Ri,
i = 0 to R−1,0 ≦ Ri <1, Ji is an integer, and an integer Ji and a decimal Ri corresponding x specification data (Ai) and variable-magnification image data calculation data (Bi) are calculated, It shall be stored in RAM3. When image reading is started, RA
The data is read from M3 and given to the sampling position designating means and the scaled image data setting means. The second calculation means is
As described above, in synchronization with the data clock DCLK, Ri (data Bi), original image data at the specified position x read from the memory means, and one or more original image data adjacent thereto are correlated with each other at the position i. The scaled image data shall be defined.

That is, in this embodiment, one line of original image data is stored in the buffer memory, and its read address is controlled to perform read sampling of the original image data,
Obtain the scaled image data. The change amount of the read address of the image data at the time of reduction, that is, the read pitch of the original image data corresponding to the scaling factor is the count clock to be given to the read address counter of the buffer memory.
It is performed by switching between DCLK and a clock 2DCLK having a frequency twice that of DCLK.

In another embodiment of the present invention, a line buffer memory is provided as in the above embodiments, but the read address is the address count means; the up / down count means; and the count data and up / down count of the address count means. It is set by adding means for giving the sum of the count data of the means to the line buffer memory as address data.

Then, the sampling position designating means gives a data clock DCLK for defining a pixel unit of the original image data as a count pulse to the address counting means when writing to the memory means, and R when reading from the memory means.
In the case of <100, the up / down counting means is instructed to up, and the data clock DCLK is given to the address counting means as a count pulse, and when Ji-Ji _-1 = 2, the data clock DCLK is also given to the up / down counting means.
When Ji ₋₁ = 1, no count pulse is given to the up / down count means, and when R ≧ 100, the up / down count means is instructed to give down and the data clock DCLK is given to the address count means, and Ji−Ji _{− When 1} = 1, the data clock DCLK is not given to the up / down counting means, and Ji−
When Ji _-1 = 0, the data clock DCLK is also given to the up / down count means to specify the read position x of the original image data.

That is, the read number x of the line buffer memory is determined by increasing or decreasing the count number of the data clock DCLK according to the scaling factor.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

FIG. 1a shows a first embodiment of the present invention, FIG. 3a shows a second embodiment, and FIG. 4 shows a third embodiment. First, the outline of these embodiments will be described.

Referring to FIG. 1a, the device shown in FIG. 1a (excluding the printer PRT) is a reading device that can be used for both digital copiers and facsimiles, and is incorporated in the exterior shown in FIG. It is what The SKYANA SCR scans A3 originals at a density of 400 dpi (pixels / inch) at 6 bits / pixel (64 gradations), performs shading correction, MTF correction, etc., and uses this 6-bit original image data for the printer. Alternatively, it is a device for converting into a binary signal / pixel of “1” or “0” for transmission and outputting. In addition,
These reading densities and gradations are examples, and 400dp
The gradation does not have to be i or 64. The document surface DOC is illuminated by the light from the light source 5, and the reflected light is reflected in the A3 document horizontal direction (297 mm).
Since it is read at 00 dpi, the image sensor 7 of 5000 pixels receives it.

The image sensor 7 converts the optical signal of the document DOC into an electric signal, and the amplifier 22 widens the signal to a signal of a predetermined level. Next, the analog signal having a different voltage level depending on the density is converted by the A / D converter 23 into a 6-bit digital signal, that is, image data.

Next, the circuit 24 performs shading correction for correcting variations in sensitivity of each element of the 5000-pixel sensor 7 and unevenness of illuminance of the light source 5 in the A3 original lateral direction.

The scaling process is performed after this shading correction in the embodiment shown in FIG. 1a. Shading correction circuit
It is also possible to carry out before 24 and after the next MTF correction circuit 29.

After the scaling process, the circuit 29 performs MTF correction, and then the binarization circuit 30 binarizes it to "1" or "0" according to the threshold level and outputs it to the printer unit or the transmission processing unit. . Alternatively, the gradation processor 31 converts the halftone expression into “1” or “0” and outputs the converted halftone expression to the transmission processing unit.
Note that FIG. 1a shows a mode of outputting to the printer PRT.

In the flow of such image data, the scaling processing is roughly shown in FIG. 1a by the parallel 6-bit latch 25 to the arithmetic unit.
28, microprocessor 35, RAM3 and sampling circuit
It is executed by a scaling processing device composed of 64 and 65.

This scaling apparatus extracts the position of the new sampling point i after scaling, the function of extracting the original image data at the original image data position x around the new sampling point i, and the new sampling point i. It has a function of calculating the scaled image data from the distance from the original image data position x (Ji) and the extracted data.

In FIG. 1a, first, the latch 25, the data distributor 26, the RAM1 and RAM2 as the line buffer memory, and the data selector 27 determine the sampling point x in the future to extract the image data and extract the scaled image data. When performing the calculation, in order to take out a plurality of original image data to be referred to in the variable-magnification image data calculation at one time, the interpolation method using the two peripheral pixels by the correction method (the embodiment shown in FIGS. 1a and 4) is 2 For each pixel, in the interpolation method using four peripheral pixels (the embodiment shown in FIG. 3a), each pixel is grouped together.

For example, when the new sampling point 0 is between Sij and Sij _{+1 in} FIG. 12, the data selector 27 selects Sij and Sij ₊₁ (see
1a and the embodiment shown in FIG. 4) or Sij _-1 , Sij, Si
This means that j ₊₁ and Sij ₊₂ are taken out at once (the embodiment of FIG. 3a).

Here, the above-mentioned method is an interpolation method (second
1a and the embodiment shown in FIG. 4), the method is an interpolation method using four peripheral pixels (embodiment shown in FIG. 3a).

As a concrete method, the original image data Y (Fig. 6) sequentially input in synchronization with the data clock DCLK is latched by the DCLK 25.
Can be implemented by using a memory (a delay memory with a DCLK1 pulse period). Two-pixel latch 25 in one stage (the embodiment shown in FIGS. 1a and 4) Four-pixel latch 25 in three stages
_{1 to} 25 ₃ (embodiment of FIG. 3a).

Next is RAM1 and RAM2 for line memory, which is a memory that stores 5000 groups of 2 pixels (the embodiment shown in FIGS. 1a and 4) or 4 pixels (the embodiment shown in FIG. 3a). The input and output have a two-stage configuration, and when one (RAM1) is an input, the other (RAM2) is an output and the input and output are reversed when one line ends. This is because the output a of the T flip-flop 36 which performs the inversion operation with the line synchronization pulse LSYNC is given to the data distributor 26, and when a is H, the data distributor 26 is used as the A output and the RAM1 is written (W). Specify and output the other output b to the data selector 27
When b is L, the data selector 27 outputs B and the RAM 2 is read (R).

Regarding the addresses of the line memories RAM1 and RAM2, at the time of input (write), the address obtained by counting up the counters 38 and 43 in the DCLK cycle is used as is, but at the time of output (read), this address is used. Change. The output address is the original image data sampling position x = Ji immediately before the sampling point i of the scaled image data.

When the sampling point i of the scaled image data is Sij and S
ij ₊₁ and the next sampling point is
When it is between Sij and Sij ₊₁ the read address counter is stopped. When it is moved between Sij ₊₂ and Sij ₊₃ , the read address counter is incremented by ₂ and between Sij ₊₁ and Sij ₊₂ . When it moves to, the read address counter is incremented by 1 as usual.

At the time of enlargement (R ≧ 100), the position of the new sampling point is determined by the operation of advancing the counter by one and the operation of stopping the counter. At the time of reduction (R <100), the position is determined by a combination of an operation of advancing the counter by 1 and an operation of advancing the counter by 2. Since the reduction is considered up to 50% in this apparatus, the counter may be incremented by one or two, but when the reduction is less than 50%, it may be incremented by three or more.

The information on where and how many read address counters to advance is calculated in advance by the microprocessor 35 by the magnification R%. Sampling point i of scaled image data
In the original image data position x immediately before, the starting position is 0, the sampling pitch P of the original image is 1, and the magnification is R.
(%), 100i / R = Ji + Ri (4) i = 0,1,2,3, ... Ji: integer, Ri: decimal integer Ji.

That is, if the sampling point i is between Sij and Sij _{+ 1} , the sampling position x of the original image data will be Ji. Therefore, as i increases, the integer part Ji of 100i / R becomes 1
When the number increases, the read address counter is also incremented by 1,
When the integer part Ji of 100i / R is increased by 2 due to the increase of i, the counter is also incremented by 2, and when the integer part Ji of 100i / R is not incremented by 1, the counter may not be incremented. . Further, the fractional part Ri of 100i / R is the distance γ ₁ between Sij and the i corresponding position 0 . This distance data γ ₁ will be used in the subsequent variable-magnification image data calculation.

The microprocessor 35 uses i = 0 to R- in the above equation (4).
Calculate up to 1. That is, the integer J ₀ by the calculation of the equation (4) when i = ₀ and the decimal R ₀ , the integer J ₁ by the calculation of the equation (4) when the i = 1 and the integer J ₁ by the calculation of the decimal R ₁ , i = 2 (4) (4) in the integer J ₂ and the decimal R ₂ , ..., i = R−1 by the calculation of the formula
Calculates the integer J _R-1 and the decimal R _R-1 by the operation of the expression. Thus, the integer Ji and the decimal fraction Ri only for i = 0 to R-1
By computing only, this can be applied to the entire line length of the original image data. That is, in all cases, the sampling points of the scaled image data have a cycle of every R, so that i =
The value of i = 0 for R, the value of i = 1 for i = R + 1, and the value of i = 1
In the case of = R + 2, the value of i = 2 may be assigned ...

In all the embodiments of the present invention described later, the calculation of Ji and Ri for i = 0 to R-1 is performed before the start of the reading operation by the magnification R.
(%) Is specified, Ji and Ri are converted into data Ai and Bi in a form matching the hardware and written in RAM3. When image reading is started, that is, during scaling processing, i is synchronized with the data clock DCLK.
Is changed to a value that is incremented by 1 and the data corresponding to i (Ai, B
i) is read from RAM3.

As another embodiment, a dedicated microprocessor or arithmetic means for performing the above calculation is provided, and the equation (4) is calculated in synchronization with the data clock DCLK in parallel with the scaling process, and an integer of 100i / R is calculated. The part Ji, that is, the original image data sampling position x may be used as the address as it is, and the decimal part Ri may be used as the distance data r ₁ which is a variable image data calculation parameter.

Next, the relationship between the reading of the original image data from the line buffer RAM1 and RAM2 and the calculation of the scaled image data will be described.

The embodiment shown in FIGS. 1a and 4 is to calculate () the scaled image data based on the original image data Sij, Sij ₊₁ and Ri of 2 pixels. In line memory RAM1 and RAM2,
The 6-bit original image data is input alternately line by line in synchronism with DCLK and latched at this input.
In addition to obtaining Sij at 25, Sij ₊₁ is obtained without passing through the latch 25, and 6-bit Sij and Sij ₊₁ are arranged side by side to obtain 12-bit data, 1-word 12-bit data in line units,
Alternately write to RAM1 and RAM2, and while writing one, data is read from the other in 1-word (12-bit) units.
₊₁ (6 bits) is given.

In the embodiment shown in FIG. 3a, latches 25 _{1 to} 25 ₃ in three stages are provided, and the latched data Sij ₋₁ , Sij and Sij ₊₁ and the data Sij ₊₂ not passing through the latches are parallel in 6 bits each. It is combined into a 24-bit word, written to RAM1 and RAM2, and read from them in parallel 24 bits simultaneously. Therefore, the arithmetic unit 28 is provided with Sij _-1 (6 bits), Sij
(6 bits), Sij ₊₁ (6 bits) and Sij ₊₂ (6 bits) are given.

The latches 25, 25 _{1 to} 25 ₃ are connected to the data selector 27 and the arithmetic unit 2
It is also possible to interpose between 8 and read / write only one line of 6-bit data from / to RAMs 1 and 2. By doing this, the transmission of the scaled image data for one line is equivalent to one pixel (in the case of FIG. 1a) or three pixels (in the case of FIG. 3a).
Although delayed, the memory capacity of RAM1 and RAM2 is 6 bits × 1 line pixel number in each case. Therefore, it is effective in reducing the line buffer memory capacity in a usage mode in which a delay deviation of several pixels does not pose a problem.

Here, when the RAM1 is in the write state (a = H, b = L), the address counter 38 advances in a cycle of DCLK in the normal operation, but the RAM1 is in the output state (a = L, A method of setting a read address for reading the image data at the sampling position x (Ji) of the original image data when b = H) will be described.

First, the first method is to change the frequency of the count clock to the address counter. If the frequency of the data clock DCLK is f ₀ , the frequency f _R
Is f _R = f ₀ · 100 / R (Hz) (5).

In this method, the deviation of f _R with respect to f ₀ is also the deviation of the sampling points of the original image and the scaled image, so that it is accurate and reliable. When reading RAM1 and 2, the address counter
The desired combined data can be obtained by operating at f _R and sampling (latching) the outputs of RAM1 and 2 with DCLK again. With this method, the information about the integer Ji in the calculation result of the above-mentioned formula (4) is unnecessary. Then,
In this embodiment, the scaling factor R% is, for example, 50 to 400%, and R
Assuming that the minimum unit of is 1%, 350 pairs of pulses f _R = f ₀ · 100
/ R is required. This is created by a dedicated microprocessor.

The second method is that the calculation result of equation (4) above is an integer.
Focusing on Ji, the previous scaling image data sampling position Xi _-1
And the sampling position Xi this time, (1) When reduced: When the integer part is increased by one (Ji-Ji _-1 = 1) Ai =
H When the integer part is increased by 2 (Ji-Ji _-1 = 2), Ai =
L (2) At expansion When the integer part is increased by 1 (Ji-Ji _-1 = 1) Ai =
H When the integer part does not increase (Ji-Ji _-1 = 0), Ai =
A sequence [Ai] of L is defined from i = 0 to R-1 and written in RAM3 (before reading). This is common to all the embodiments of FIGS. 1a, 3a and 4.

Then, in the embodiment of FIG. 4, as the count pulse,
Data clock DCLK and pulse 2D with twice the frequency of DCLK
Prepare CLK. Ai is RAM3 when calculating scaled image data
From i, read is repeated from i = 0 to R-1. In the embodiment shown in FIG. 4, the reduction time (R <10
0), the count pulse of the address counter (38 or 43) for reading the line memory (RAM1 or RAM2) is switched so as to be DCLK when Ai = H and 2DCLK when Ai = L. When expanding (R ≧ 100), the count pulse of the address counter 38 or 43 is Ai and DCLK.
By using AND (logical product), the count-up is performed when Ai = H and the count is not performed when Ai = L.

All the embodiments of the present invention have RAM3, which is based on the result of the equation (4) calculated by the microprocessor 35.
To store. The RAM 3 also stores data Bi that is different in each embodiment. The contents of Bi will be described later.

In this way, if Ai is stored in RAM3 before image reading and this is read during image reading and a read address is set based on Ai, adjacent data Sij and Sij _{+ 1} are simultaneously read from RAM1 and RAM2. (Embodiments of FIGS. 1a and 4), or at the same time, the adjacent data Sij _-1 , Sij, Sij ₊₁ and Sij ₊₂ (embodiment of FIG. 3a) will be read together with being read out later. As described above, the configuration of the calculator 28 that calculates the scaled image data is simplified.

In the count pulse switching method of the embodiment shown in FIG. 4, when the enlargement (R ≧ 100) and Ai = L, the ENABLE of the counters 38 and 43 is enabled.
The terminal may be set to L to stop counting.

The third method is carried out in the embodiment shown in FIG. 1a. The address counters 38 and 43 themselves use the data clock DCL.
Continue counting up by K. In addition to the address counters 38, 43, another up / down counter 39, 44 is provided to specify down when expanding (R ≧ 100) and up when reducing (R> 100). Then, the up / down counters 39 and 44 input the AND (logical product) of DCLK and Ai so as to count only when Ai = L.

As a result, for example, at the time of reduction, first, the up / down counters 39 and 44 are set to 1 when Ai = L, the adders 37 and 42 add 1 to the values of the address counters 38 and 43, and the RAM1 and RAM2 are read. Address. Further, at the next Ai = L, the up / down counters 39 and 44 are set to 2, and the count values of the address counters 38 and 43 are added to determine the position x (Ji) of the sampling point.

In the case of enlargement, it is necessary to read the read address without shifting it. At this time, since the address counters 38 and 43 count up, to compensate for this, conversely, subtract one by one with Ai = L. The up / down counters 39 and 44 are decremented.

Next, a method of calculating the scaled image data will be described. 1a
In the embodiment shown in the figure, the above-mentioned method is executed by the arithmetic unit 28 (details are shown in Fig. 1b), and in the embodiment shown in Fig. 3a, the above-mentioned method is executed. A method of executing these methods will be described.

Proximity pixel distance linear allocation method (FIGS. 1a and 1b) This method performs the calculation of the above-mentioned expression (1). In this case, the problem is the accuracy of the distance r ₁ / P or r ₂ / P. It is up to the first decimal place, that is, it is better to think in 0.1 steps or to see it in more detail, or to divide P into 4 parts, that is, 0.25 steps. This problem is how much accuracy is required as a digital copier system or a facsimile system, and corresponds to the required image quality in the digital copier or facsimile system. As seen from the arithmetic processing, it is preferable that r ₁ / P and r ₂ / P are reciprocal powers of two. This is because operations such as 1/2, 1/4, 1/8, etc. can be performed only by bit shifting the target data. Therefore, first, Ri = r ₁ / P is set to 0.25 (1/4) from the calculation result of equation (4).
Divide into small pieces. That is, the minimum unit of Ri is 1/8 and the area division of Ri is 1/4. As an example, try dividing as follows.

When 0 ≦ r ₁ / P <1/8, Ri = r ₁ / P = 0, Bi = 0 1/8 ≦ r ₁ / P <3/8, Ri = r ₁ / P = 1/4 , Bi = 1 3/8 ≦ r ₁ / P <5/8, Ri = r ₁ / P = 1/2, Bi = 2 5/8 ≦ r ₁ / P <7/8, Ri = r ₁ / P = 3/4, Bi = 3 Here, when 7/8 ≦ r ₁ / P <1, it means that 0 and Sij ₊₁ are at the same position. = 4
However, in this case, since 3 bits are required for Bi, in this case, from the hardware configuration, x is incremented by 1, the integer Ji is increased by 1 and the decimal fraction Ri is set to 0.
Then, it is preferable that 0 is between Sij ₊₁ and Sij ₊₂ and Bi = 0, since Bi can be a 2-bit signal. Similar to the above, this Bi is written together with Ai at the same address in RAM3.

In the arithmetic unit 28 of FIG. 1a (FIG. 1b) for implementing this method, A.Sij ₊ B.Sij _{+ 1 + 1} = 0ik (6) where A is calculated according to the distance (Bi = 0-4) divided into four. Is a coefficient corresponding to r ₁ / P, B is a coefficient corresponding to r ₂ / P, Sij and Sij ₊₁ are contents of 6-bit data, and 0ik is contents of scaled image data (6 bits).

Since A and B are decided, there are 4 ways of A ・ Sij and B ・ Sij ₊₁
, And select one by one for Bi-compatible data selector
28b, 28c, adder 28d to select the scaled image data
Get 0ik.

In the embodiment shown in FIG. 1a, the coefficients A and B corresponding to Bi are
Are set as shown in Table 1 below.

Since the reciprocal of a power of 2 such as 1/2, 1/4 can be obtained only by bit shifting the signal line, the hardware configuration becomes very easy.

Cubic function convolution This method requires extremely complicated calculation as shown in the above equation (3) and is not suitable for hardware implementation. You can double.

There is the same problem of distance accuracy as in the case of this system, but here also consider the case where γ ₁ / p is divided into four.

The division method is exactly the same.

If the above formula (3) is simply rewritten, A · Sij ₋₁ + B · Sij + C · Sij ₊₁ + D · Sij ₊₂ = 0ik ...
(7) Note that the denominator of equation (3) is a normalization coefficient and can be excluded from the parameters.

From the above equation (2), A, B, C and D are calculated in the four cases of γ ₁ / P = 0, 1/4, 1/2, 3/4 as follows.

Based on this coefficient, four kinds of A · Sij ₋₁ , B · Sij, C · Sij ₊₁ and D · Sij ₊₂ are provided in the same manner as the computing unit 28 of FIG.
(Sij etc. is 0 to 63), there is a method of selecting one by one with Bi and adding four. However, in this case, unlike in the case of, each calculation is slightly troublesome, and the hardware becomes a little complicated. Therefore, in order to reduce the load on the hardware as much as possible, the coefficients A, B, C and D are approximated as shown in Table 2 below and rewritten. However, at this time, it is necessary that A + B + C + D = 1.

In this case, the denominator of the coefficient is 8 or less, and the counting by hardware becomes much easier. In the embodiment shown in FIG. 3a, the scaled image data is calculated by using the coefficients in Table 2.

Next, the hardware configuration and operation of the embodiment of the present invention will be described.

First embodiment (FIGS. 1a, 1b and 2a, 2b,
2c) In the first embodiment shown in FIG. 1a, the original image data read by the scan scanner SCR is sent to the shading correction circuit 24 for each line, and parallel 6 bits (6 bits are 1 The line sync pulse LSYN is supplied serially in units of 1 word indicating pixel density), and the circuit 24 has a similar data structure and a similar transfer format.
One line is supplied to the latch 25 and the data distributor 26 in synchronization with the data clock DCLK for one line during one cycle of C. The output of the circuit 24 is the data of a pixel
When Sij _{+ 1} , the output of the latch 25 is the data Sij one pixel before, and these data Sij and Sij _{+ 1} are given to the data distributor 26 in parallel 12 bits.

On the other hand, the T flip-flop 36 outputs the line synchronization pulse LSYN.
Since the signal level of its output Q, Q is inverted every time one pulse of C arrives, for example, when the data of the first line is given, the data distributor 26 gives the input 12 bits to RAM1 and RAM1. Is designated for writing. At this time, the data selector 27 gives the 12-bit data of the input terminal B to the arithmetic unit 28, and the RAM 2 is designated for reading. When the data of the second line is supplied to the data distributor 26, the data distributor 26 supplies the input 12 bits to the RAM2, and the RAM2 is designated for writing. At this time, the data selector 27
12-bit data is given to the arithmetic unit 28, and RAM1 is designated for reading.

In this way, the data of the adjacent two pixels of the nth line are written in parallel to the RAM1, while the data of the adjacent two pixels of the n-1th line are read out in parallel from the RAM2. The data of the adjacent two pixels of the (n + 1) th line are written in parallel to the RAM2, while the data of the adjacent two pixels of the nth line are read from the RAM1 in parallel. Similarly, RAM1 and RA
M2 is switched by the line synchronization pulse LSYNC and alternately designated for writing and reading. In this way, the data of two adjacent pixels on the n-th line are combined in parallel.
When writing the bit data into RAM1 or RAM2, 12-bit data obtained by combining the data of the adjacent two pixels of the (n-1) th line in parallel is read from RAM2 or RAM1 and given to the arithmetic unit 28. That is, the arithmetic unit 28 includes the circuit 24
The original image data is provided in a form in which the data of two adjacent pixels are arranged with a delay of one line from the data output by. In this way, the data reading from the buffer memories RAM1 and RAM2 is delayed by one line from the input to the buffer memories RAM1 and RAM2.

The read / write address of RAM1 is determined by the sampling circuit 64, and the read / write address of RAM2 is determined by the sampling circuit 65.

First, the sampling circuit 64 will be described. When the RAM 1 is designated for writing, the signals a = H, b = L, the AND gate 40 is off (gate closed), and the up / down counter 39 receives a count pulse. If not given, its output remains at 0. Since the data clock DCLK is given to the address counter 38 as a count pulse, it is incremented by 1 each time one pulse of the data clock DCLK arrives. The adder 37 adds the count data of the counters 39 and 38 and gives the sum data to the RAM 1 as address data. As a result, the 12-bit data obtained by parallelizing the data of two adjacent pixels becomes the data clock.
Data is sequentially written to RAM1 in synchronization with DCLK. Ie 1
All data for the line is written to RAM1.

When RAM1 is designated for reading, a = L, b =
Since it is H, the AND gate 40 is turned on (gate is opened) when the signal c is L, and the up / down counter 39 is supplied with the data clock DCLK as a count pulse. Signal d
= H (reduction), up-counting, and d = L (enlargement), down-counting. The signal c is the data Ai described above and controls the stop / progress of counting. At the time of reading, the sum of the count values of the counters 39 and 38 becomes the read address of the RAM1. c =
In the case of L, the counter 39 counts up by 1 every time DCLK appears 1 pulse when d = H, and the read address of the RAM 1 advances by 2, and the counter 39 appears each time DCLK appears 1 pulse when d = L. 1 countdown, RA
Note that the read address of M1 stalls.

c = Ai.

The sampling circuit 65 has exactly the same configuration as 64, except that the a signal is applied to the AND gate 45 instead of the b signal. This is because when RAM1 is read (b = H, a = L), RAM2 is write and RAM1 is written (b = L, a).
This is because the RAM 2 is read out when H = H) and the read address is the sum of the count values of the counters 44 and 43.

Here, Ai will be described. The microprocessor 35
In response to the image reading start instruction (ST changes from L to H), the specified scaling ratio R% is read, and based on this, i
= 0 to R−1, Ji and Ri are calculated, and when R <100 (reduction), Ji−Ji ₋₁ ≧ 2 and Ai is L
Ai is H when Ji-Ji _-1 ≤1, and when R ≥ 100 (enlarged), Ai is H when Ji-Ji _-1 ≥ 1 and Ai when Ji-Ji _-1 ≤ 0
Is set to L, position difference data Bi (Table 1) is set in correspondence with Ri, and Ai and Bi are stored in the RAM at address R-i. In this memory operation, the microprocessor 35
Is, i = 0 data A ₀ and B ₀ corresponding giving one pulse to the OR gate 49 before writing, loading data representing the R in the address counter 48. When A ₀ and B ₀ are given to the RAM 3, one pulse is given to the OR gate 51, the address counter 48 is incremented by 1, and the data A ₁ corresponding to i = ₁
And B ₁ are applied to RAM 3 and then one pulse is applied to the OR gate 51. Such an operation is performed until i = R-1. Accordingly, the data A ₀ and B ₀ i = 0 corresponding to the address 0 of the RAM 3, the address 1 i = 1 corresponding data A ₁ and B
₁ is ... Data A corresponding to address R-1 at i = R-1
_R-1 and BR _-1 will be written.

Then, when the image reading is instructed to the scanning SCR and the image reading is actually started, the data indicating the designated magnification R% is set in the address counter 48 by the line synchronization pulse LSYNC, and every time the data clock DCLK appears one pulse. The counter 48 increments by 1 and the read address is incremented by 1 each time DCLK appears, i =
0 corresponding data A ₀ and B ₀ to i = R-1 corresponding data
A _R-1 and B _R-1 are sequentially read, the data Ai is given to the sampling circuits 64 and 65 as a signal c, and the data Bi is given to the data selectors 28b and 28c of the arithmetic unit 28.

The data selector 28b has a coefficient A corresponding to Bi (Table 1).
The data obtained by multiplying Sij (Table 1) by the data selector 2
8c supplies the data obtained by multiplying Sij ₊₁ by the coefficient B corresponding to Bi to the adder 28d, and the adder 28d outputs the data indicating the sum thereof as the scaled image data 0ik. This output operation is synchronized with the data clock DCLK.

The scaled image data 0ik is supplied to the MTF correction circuit 29, and the circuit 29
To the binarization circuit 30 and the gradation processor 31. In this embodiment, the gradation processor 31 includes 64 kinds of ROMs having gradation distribution data distribution patterns corresponding to density, a cyclic line counter initialized by 64 counts, and cyclic data initialized by 64 counts. It has a clock counter, and the read address of the ROM is 0i
k, line count data and data clock count data. That is, one pattern of the ROM is specified by 0ik, the main scanning address of the pattern is specified by the data clock counter, and the sub-scanning address of the pattern is specified by the line counter, and the 1-bit image data in the pattern is read. When the microprocessor 35 gives an instruction to output the binarized data (i = H), the gate circuits 32 to 34 give an instruction to output the binarized circuit 30 and output the gradation data (i = H).
In the case of L), the output of the gradation processor 31 is output to the printer PRT.

Next, the scaling processing control operation of the microprocessor 35
Description will be given with reference to FIGS. 2b and 2c. First 2a
Refer to the figure.

Microprocessor when power is turned on (step 1)
Reference numeral 35 sets the input / output port to the standby state level and clears the internal registers, counters, timers, flags, etc. (step 2: hereinafter, the word step is omitted in parentheses).

Next, the data R designating the designated scaling ratio R% is read and stored in the register Rs (3), and L is set to the output port g (4). That is, the AND gate 50 is turned off (gate closed), and the address counter 48 is set so that the count pulse is not given from the outside. Next, output port n
Then, the data indicating the designated scaling ratio Rs% stored in the register Rs is set (5) and added to the preset data input terminal P of the address counter 48. Then, one pulse is output to the output port f (6) and the address counter 48 is loaded with Rs. As a result, the address counter 48 is initialized (initial address setting). Next, the microprocessor 35 sets the RAM 3 for writing (7) and sets the contents of the internal address register i to indicate 0 (register clear) (8). As a result, the above i = 0 is set. Then clear register j, register
Set H on Bi and Ai (9). Then, the contents Bi and Ai of the registers Bi and Ai are stored in the RAM 3 (10). At this stage, since i = 0, B ₀ is assigned to the address R of RAM3.
= H and A ₀ = H have been written. Next, the content of the register i is incremented by 1 (11). This means that the value of i has been changed to a value one greater than the previous value.
Next, since i is 2 or more (2 at this stage), 100i
Calculate the integer Ji and the decimal number Ri that are / Rs = Ji + Ri (13),
The contents of the present calculation value register ji are transferred to the last calculation value register ji _-1 (14a), the integer Ji is stored in the present calculation value register ji (14b), and then in steps 41 to 50 of FIG. 2b, Bi
And set Ai in steps 18 to 25. Then, one pulse is output to the output port h (22), the write address of the RAM3 is incremented by one, the write address is advanced, and in step 10, the set Bi and Ai are written in the RAM3. Similarly, change i to a value that is 1 larger (11),
Ji and Ri are calculated (13), Bi and Ai are set based on them and Rs (41 to 50 in Fig. 2b), the write address of RAM3 is updated (22), and Bi and Ai are stored in RAM3. Write (1
0). In this way, when i = Rs + 1, i = 0 to R
Since all Bi and Ai corresponding to s-1 have been written in the RAM 3, the process proceeds from step 12 to the variable magnification processing control at the time of image reading in FIG. 1c. Note that steps 8 to 9
At the time of proceeding to, the address 0 of RAM3 is written with A ₀ = H, but this does not correspond exactly to Ji-Ji _-1 . Because Ji _-1 is unknown at this stage. However, when i is set to Rs−1, the counter 48 is initialized by a carrier indicating the Rs countover of the counter 48 next (i = Rs) and i is reset to 0. Therefore, i = 0 and i = Rs Is the same. Therefore, the operation of A _{0 at} i = 0 can be replaced with that of i = Rs. Then J _{R -1} when i = Rs _-1 is J i _-1
Can be used as. Therefore, in step 12, it is checked whether the calculation of Ai and Bi and the memory to RAM3 have been completed until i = Rs. That is, it is sufficient to store Ai and Bi from i = 0 to Rs-1, but further i = Rs (this is synonymous with i = 0)
Ai and Bi are calculated and stored in memory. This i = Rs
Then, since the counter 48 counts over Rs and sets the write address of RAM3 to 0, the data is written in step 9.
B ₀ and A ₀ will be rewritten as B _R s, A _R s. As a result, A ₀ written in steps 9 and 10 is updated to an accurate value.

When the process proceeds to step S12 in FIG. 2c, the image reading start instruction signal ST waits for the image reading start instruction signal ST to become H (26), and the reading start instruction is not received. , Reads the input magnification instruction data R and checks whether it is the same as the value stored in the register Rs (27). If they are not the same, the designated magnification R has been changed, so return to step 3 in FIG. 2a, and similarly, calculate the data Bi and Ai corresponding to the new designated magnification R and write them to the RAM3. To do.

When the image reading start instruction signal ST goes high, the scan SC
Check if R is ready (28), check if printer PRT is ready (29), and wait for both to become ready if either is not ready.

If both SKYANA SCR and printer PRT are ready, 2
If value image processing (document: text image processing) is instructed, set H to the output port i (31) 2
The gate circuits 32 to 34 are set so as to give the output of the binarization circuit 30 to the printer PRT, and when gradation image processing (photographic image processing) is instructed, L is set to the output port i (32 The gate circuits 32 to 34 are set so that the output of the gradation processor 31 is given to the printer PRT. Next, the microprocessor 35 refers to the content of the designated scaling register Rs to check whether reduction is designated or enlargement is designated (33), and when reduction is designated, the output port d
Is set to H (34), and the up-down counters 39 and 44 are set to up-count. When enlargement is designated, L is set to the output port d (35) and the up / down counters 39 and 44 are set to down count.

Next, the RAM 3 is set to read (36), H is set to the output port g (37), and the AND gate 50 is turned on (gate open). Next, an H-level start signal ATS is given to the scan SCR and printer PRT (38).

Scanner SCR starts image reading in response to ATS going high, and outputs line sync pulse LSYNC, data clock DCLK, and original image data serially line by line. For example, odd line data Is written to RAM1,
When the even line data is written to RAM2 and the odd line data is written to RAM1, the even line data is read from RAM2 and the even line data is
When written to RAM2, the odd line data is RA
Read from M1. That is, the original image data is written in the line buffer memories RAM1 and RAM2 in the form shown in FIG.
Also read from it.

During this image reading, the address counter 48 is initialized by the line synchronization pulse LSYNC and the count-over signal generated by itself (generated every time when the numerical value of the specified magnification Rs% is counted), and then the data clock DCLK.
To count up. This allows the address counter 48
The address given to RAM3 becomes 0 when the line synchronization pulse LSYNC arrives for one pulse, and sequentially increases by 1 every time one pulse of DCLK appears. Next to the maximum number RS-1, the address counter 48 It is set to 0 again by the initialization due to the count-over, and becomes 1 every time DCLK arrives. This is repeated during one cycle of the line sync pulse LSYNC. RAM3 is set to read, so Ai
And Bi, i = 0 to R−1 are sequentially read from RAM3 from i = 0, and when i = R−1, they are read from i = 0, and so on. Ai is read as a signal c to the inverters 41 and 46,
Bi is provided to the data selector 28a.

c = Ai = H (Ji- Ji -1 ≦ 1 at reduced early days, enlarged at Ji-Ji _-1 ≧
In the case of 1), since the AND gates 40 and 45 are turned off (gate closed), the count values of the counters 39 and 44 do not move,
The scaled image data is sampled at the same sampling pitch as the sampling pitch (P = 1) of the original image data. In this period, the image magnification is 1. That is, the scaled image data becomes the original image data (not thinned out or written twice).

c = Ai = L (Ji-Ji _-1 ≧ 2 when reduced, Ji-Ji _-1 <when expanded
In the case of 1), since the counters 39 and 44 are up-counting at the time of reduction, since the counters 39 and 44 are counting up in the same way as the address counters 38 and 43 are counting up, one pulse of DCLK Upon arrival, the read addresses of RAM1 and RAM2 are increased by 2, and the original image data is sampled in every one pixel. Counter when expanding
Address counter 3 because 39 and 33 are down-counting
Since counters 39 and 44 count down in contrast to 8 and 43 count up, the read address of RAM1 and RAM2 does not move even when DCLK arrives, and the data of the same pixel of the original image data should be repeatedly sampled. become.

By the above sampling operation, the original image data is sampled at the pitch corresponding to the designated magnification R.

In FIG. 1b showing the configuration of the arithmetic unit 28 of FIG. 1a,
28 calculates the scaled image data 0ik as described above.

That is, the four types of coefficients A and the image data Sij (0
˜63) is applied to the input ports a to d of the data selector 28b. Note that a to d correspond to a to d in the right column of Table 1, where a is all bits of Sij, that is, Sij, and b is the sum of upper 5 bits and upper 4 bits of Sij. The data shown is the top 5 of Sij in c.
Bits, that is, 1/2 Sij, are given to d, and the upper 4 bits of Sij, that is, 1/4 Sij.

Further, the data obtained by multiplying the four types of coefficients B in Table 1 by the image data Sij ₊₁ is the input ports a to d of the data selector 28c.
Applied to. Note that these a to d are also a to d in the right column of Table 1.
Data corresponding to 0, a indicating 0, and b indicating
The upper 4 bits of Sij _{+ 1} , that is, 1 / 4Sij _{+ 1,} is assigned to c as Sij _{+ 1}
Of the upper 5 bits of Sij ₊₁ , ie, 1 / 2Sij ₊₁ is given, and d is given data indicating the sum of the upper 5 bits of Sij ₊₁ and the upper 4 bits of data, namely 3 / 4Sij ₊₁ .

The outputs A and B of the data selectors 28b and 28c are set to any one of the inputs a to d by the signal Bi applied to them, and when the data Bi is 0, the input a is set to the outputs A and B, When the data Bi is 1, the input b is the outputs A and B, and when the data Bi is 2, the input b is
When the input c is the output A, B and the data Bi is 3, the input d is the output A, B. The values of Bi are shown in Table 1.

The adder 28d converts the data indicating the sum of the output A of the data selector 28b and the output B of the data selector 28c to the scaled image data 0ik.
Output as.

The selection data Bi of the data selectors 28b and 28c is stored in RAM3,
It is pre-read before the image is read.

In steps 41 to 50 of FIG. 2b, the data Bi (of Table 1) is set for calculating the scaled image data by. That is, the decimal number calculated with each value of i
Ri is 0 ≦ Ri <1/8, 1/8 ≦ Ri <3/8, 3/8 ≦ Ri <5/8, 5/8 ≦ Ri <7 /
Step 8 to see if 8, or 7/8 ≤ Ri <1,
Check with 1 to 47, and if 0 ≦ Ri <1/8, register Bi
The data indicating 0 is set to (42), and when 1/8 ≦ Ri <3/8, the data indicating 1 is set to the register Bi (44), 3 /
When 8 ≦ Ri <5/8, data indicating 2 is set in the register Bi (46), and when 5/8 ≦ Ri <7/8, data indicating 3 is set in the register Bi (48). When 7/8 ≦ Ri <1, Ri is rounded up to 1, the content of the register j is updated by a number larger by 1 (49), and 0 is set in the register Bi.
The Bi thus set is written in the RAM 3 together with Ai.

During image reading, the data Bi set in this way is read from the RAM 3 together with Ai and given to the data selectors 28b and 28c. As a result, the scaled image data 0ik output from the adder 28d is calculated by the above-described equation (6).

Second Embodiment (FIGS. 3a and 3b) FIG. 3a shows only the constituent parts of the second embodiment that differ from the first embodiment, and only the parts that differ from the processing control operation of the first embodiment. Is shown in FIG. 3b. This second embodiment is based on the latch 25 of FIG. 1a.
3 rows 25 _{1 to} 25 ₃ and 4 adjacent Si of the original image data
j _-1 , Sij, Sij ₊₁ and Sij ₊₂ are arranged in parallel and given to the line memories RAM1 and RAM2. In addition, the calculator 28
Also differs from the first embodiment.

In FIG. 3a, the calculator 28 calculates the scaled image data 0ik as described above.

That is, the data obtained by multiplying each of the four types of coefficients A in Table 2 by the original image data Sij ₋₁ is supplied to the data selector 52.
The data obtained by multiplying each of the four types of coefficient B in Table 2 by the original image data Sij is the data obtained by multiplying the data selector 53 by each of the four types of coefficient C in Table 2 by the original image data Sij _+1. Is given to the data selector 54, and the data obtained by multiplying each of the four types of coefficients D in Table 2 by the original image data Sij ₊₂ is given to the data selector 55.
Each of the 55 outputs data indicating the value calculated by one of the coefficients A to D (each of 4 types: Table 2) specified by the data Bi (Table 2), and the sum obtained by adding them is The scaled image data 0ik is output from the adder 56.

The complementer 57 is for converting the subtraction data (-1/8) into addition data (converting subtraction into addition).

The outputs A to D of the data selectors 52 to 55 are set to any one of the inputs a to d depending on the signal Bi given to them, and when the data Bi is 0, the input a is output A to D.
When the data is D and Bi is 1, the input b is the outputs A to D, when the data Bi is 2, the input c is the outputs A to D, and when the data Bi is 3, the input c is the outputs A to D. , Input d is output A to D. The values of Bi are shown in Table 2.

The adder 56 outputs the data indicating the sum of the outputs A to D of the data selectors 52 to 55 as the scaled image data 0ik.

The selection data Bi of the data selectors 52 to 55 is previously read in the RAM 3 before the image is read.

The scaling control operation of the microprocessor 35 of the second embodiment (FIG. 3a) is substantially the same as that of the first embodiment shown in FIGS. 2a, 2b and 2c, but Figure steps
Data for calculation of scaled image data according to 41 to 50
Instead of Bi setting, as in steps 41 to 50 shown in FIG. 3b,
The data Bi (shown in Table 2) for variable-magnification image data calculation is set. That is, the decimal number Ri calculated with each value of i is 0 ≦ Ri <1/4, 1/4 ≦ Ri
<1/2, 1/2 ≤ Ri <3/4, 3/4 ≤ Ri <7/8, and 7/8 ≤ Ri <
Check which one is in step 41 to 47,
When 0 ≦ Ri <1/4, data indicating 0 is set in the register Bi (42), and when 1/4 ≦ Ri <1/2, data indicating 1 is set in the register Bi (44), When 1/2 ≤ Ri <3/4, set the data indicating 2 to register Bi (46), and 3/4 ≤ Ri
When <7/8, data indicating 3 is set in the register Bi (48). When 7/8 ≦ Ri <1, Ri is rounded up to 1 and the content of register j is updated to a number one larger (49),
0 is set in the register Bi. Bi set like this
Is written in the RAM 3 together with Ai as in the first embodiment.

The other scaling processing control operation is similar to that of the first embodiment, and during the image reading, the data Bi set in this way is Ai.
At the same time, it is read from the RAM 3 and given to the data selectors 52 to 55. As a result, the scaled image data 0ik output from the adder 56 is roughly calculated by the above equation (7).

Third Embodiment (FIG. 4) FIG. 4 shows only the components of the third embodiment that differ from the first embodiment. In the third embodiment, the sampling circuit 64 and
65, and other portions are the same as those in the first embodiment, and portions other than the sampling circuits 64 and 65 may be the same as those in the second embodiment.

The sampling circuit 64 shown in FIG. 4 has an AND gate 68 when the RAM 1 is designated for writing (a = H, b = L).
Since and 69 are off and the AND gate 67 is on, the address counter 38 is counted up by DCLK. That is, the original image data is read into the RAM1 every time one pulse of DCLK arrives. When the RAM1 is designated for reading (a = L, b = H), the AND gate 67 is off, and when the RAM1 is reduced (d = H), the AND gate 68 is also off, and the data Ai is stored. Correspondingly, when it is H, DCLK
2DCLK when Ai is L, AND gates 71 and 72
And to the counter through OR gate 70 and AND gate 69 and OR gate 66. When enlarged (d = L), AND gate 69 is off, and when Ai is H, DC
LK is supplied to the counter 38 through the AND gate 68 and the OR gate 66, and when Ai is L, the clock is not supplied to the counter 38.

The sampling circuit 65 also has the same configuration as 64, but the signals a and b are exchanged and supplied to the AND gates 74, 75 and 76. This is because RAM2 is read when RAM1 is written and RAM2 is written when RAM1 is read.

With the configurations and operations of the sampling circuits 64 and 65 described above, also in the third embodiment, in the same manner as in the first embodiment (FIG. 1a), writing to the RAMs 1 and 2 and reading and sampling from the RAMs 1 and 2 are performed. . That is, in the first embodiment, the up-down counters 39 and 44 and the adders 37 and 42 count the sampling of the original image data, which is skipped one by one, by double counting DCLK to set the address to 1 of DCLK. The number of pulses is increased by 2 per pulse, but in the third embodiment, in this case, 2D
CLK is given to the address counter, and when the DCLK generates one pulse, the address counter is incremented by 2,
The address is advanced by 2 per 1 pulse of DCLK.

In all the embodiments described above, the magnification is changed in the main scanning direction X. The scaling in the sub-scanning direction Y is 100Li / R = Lj + Lr, where Li is the scaling image data sampling line No., Lj
Is an integer, Lr is a decimal number, and an integer Lj and a decimal number Lr are calculated. When Lr is 0.5 or less, the Lj line data of the main scanning direction scaled image data described above is calculated. When Lr is greater than 0.5, The data of the (Lj _{+ 1) th} line may be extracted as the Lith of the final scaled image data that has been scaled in the main scanning direction and the sub-scanning direction. This extraction is, in the above-mentioned embodiment,
The printer PRT refers to the magnification data R to perform the processing. In addition, the scaling process in the sub-scanning direction may be performed in the same manner as the scaling process in the main scanning direction described above. The scaling process in the sub-scanning direction
The line synchronization pulse LSYNC is used in place of DCLK with the same hardware as the hardware for the scaling processing in the main scanning direction described above. The latches 25, 25 _{1 to} 25 ₃ may be changed to line buffers, which are shift-energized by DCLK.

As described above, according to the present invention, 100i / [specified magnification R
(%)] = Ji + Ri, i is an integer, 0 ≦ Ri <1, Ji is an integer, and an integer Ji and a decimal number Ri are calculated, and data Bi that represents the decimal number Ri as a denominator of a power of 2 is calculated. First computing means for changing the i by 1 in synchronization with a data clock that defines the pixel unit of the original image data, and if R <100, Ji
When -Ji _-1 = 2, the sampling designated position x of the original image data is designated to be a number larger by 2 and when Ji-Ji _-1 = 1 is designated to the designated position x is designated to be a number larger by 1; -Ji _-1 = 1 and the sampling position designating means for designating the position x to be a number larger by 1 and Ji-Ji _-1 = 0 to the position x as it is; counting the data clock to count the designated position x Sampling means for extracting the original image data and one or more image data adjacent thereto, and the original image data at the designated position x and the one or more original image data adjacent thereto in bit units in synchronization with the data clock. Second input means configured to use the bit shift to input the plurality of original image data and to calculate the scaled image data by a coefficient whose denominator is a power of 2 corresponding to the data Bi. , High precision, fine It is possible to perform a wide range of magnification in real time, and it is possible to simplify the configuration of the second arithmetic means for zooming.

[Brief description of drawings]

FIG. 1a is a block diagram showing the configuration of the first embodiment of the present invention. FIG. 1b is a block diagram showing the configuration of the arithmetic unit 28 shown in FIG. 1a. FIGS. 2a, 2b and 2c are flow charts showing the scaling control operation of the microprocessor 35 shown in FIG. 1a. FIG. 3a is a block diagram showing an essential part of the second embodiment of the present invention. FIG. 3b is a flow chart showing a part of the scaling processing control operation of the microprocessor 35 shown in FIG. 3a. FIG. 4 is a block diagram showing the main part of the third embodiment of the present invention. FIG. 5 is a graph showing the value of the interpolation function used in the cubic function convolution method for calculating the scaled image data, where the horizontal axis represents the sampling position assigned to the scaled image data with respect to the sampling position of the original image data. The amount of deviation is shown, and the vertical axis shows the value of the interpolation function. FIG. 6 shows the data Y which is the image reading output of the scan SCR shown in FIG. 1a, the synchronizing clocks LSYNC, DCLK and the latch 25.
3 is a time chart showing the relationship of the data Z which is the output of FIG. FIG. 7 shows the line buffer memory RAM1, RAM shown in FIG. 1a.
2 write data, read data and line sync pulse L
It is a time chart showing the relationship with SYNC. FIG. 8 is a perspective view showing the appearance of a conventional image reading apparatus. FIG. 9 is a side view showing main mechanical components of one conventional image reading apparatus. FIG. 10 is a side view showing main mechanical components of another conventional image reading apparatus. FIG. 11 is a plan view showing the image data distribution on the memory corresponding to images when original image data for one page is stored in the memory for image data scaling by the conventional electrical method. . FIG. 12 is a plan view showing the relationship between the sampling position of the original image data and the sampling position of the scaled image data when the scaled image data is calculated by the distance linear distribution method between adjacent pixels. 1: Image reading device, 2: Contact glass plate 3: Original pressure plate, 4: Operation part 5: Fluorescent lamp, 6: Selfoc lens, 7: Image sensor, 8: Reflected light 9: Carridge, 11 to 13: Reflected light 14 : Lens, SCR: Scan DOC: Original 35: Microprocessor (calculation means, sampling position designation means) 64,65: Sampling circuit (sampling means) (28, RAM3, 35: Scaled image data setting means)

Claims (3)

[Claims] 1. An integer Ji and a decimal fraction Ri, wherein 100i / [specified magnification R (%)] = Ji + Ri, i is an integer, 0 ≦ Ri <1, Ji is an integer, and this decimal fraction Ri is raised to a power of 2. First computing means for computing the data Bi represented by the denominator area division; i is changed one by one in synchronization with the data clock defining the pixel unit of the original image data, and if R <100, Ji
When -Ji _-1 = 2, the sampling designated position x of the original image data is designated to be a number larger by 2 and when Ji-Ji _-1 = 1 is designated to the designated position x is designated to be a number larger by 1; -Ji _-1 = 1 and the sampling position designating means for designating the position x to be a number larger by 1 and Ji-Ji _-1 = 0 to the position x as it is; counting the data clock to count the designated position x Sampling means for extracting the original image data and one or more image data adjacent thereto, and the original image data at the designated position x and the one or more original image data adjacent thereto in bit units in synchronization with the data clock. A second arithmetic means configured to use the bit shift so as to arithmetically operate the scaled image data by inputting the plurality of original image data with a coefficient whose denominator is a power of 2 corresponding to the data Bi. Data scaling Apparatus. 2. Memory means for storing original image data for one line; means for alternately setting the memory means for writing / reading; address counting means for giving a writing / reading position x to the memory means; 100i / [ Specified magnification R (%)] = Ji + Ri, i is an integer, 0 ≦ Ri <
1, Ji is an integer, the integer Ji and the fractional Ri are calculated, and the data that represents the fractional Ri with the power of 2 as the denominator
First computing means for computing Bi; when writing to the memory means, the data clock DCLK that determines the pixel unit of the original image data is given to the address counting means as a count pulse, and when reading from the memory means, the data clock DCLK I is changed by 1 in synchronism with, and when R <100, when Ji-Ji _-1 = 2, count pulse 2DCL with double frequency of data clock DCLK
When K is Ji-Ji _-1 = 1 and the data clock DCLK is given to the address counting means as a count pulse, when R ≧ 100, Ji-Ji _-1 = 1 is given the data clock DCLK to the address counting means, When Ji-Ji _-1 = 0, the sampling pulse is cut off to the address counting means to specify the reading position x of the original image data; and the specified position x is synchronized with the data lock. The original image data and one or more original image data adjacent thereto are input in bit units, and the plurality of original image data are input to the data.
An image data scaling processing apparatus comprising: a second arithmetic means configured by bit shift so as to compute scaled image data by a coefficient whose denominator is a power of 2 corresponding to Bi. (7) Memory means for storing original image data for one line; means for alternately setting the memory means for writing / reading; address counting means; up / down counting means; count data of address counting means And an adding means for giving the sum of the count data of the up / down count means to the memory means as address data; 100i / [specified magnification R (%)] = Ji + Ri, i is an integer, 0 ≦ Ri <
1, Ji is an integer, the integer Ji and the fractional Ri are calculated, and the data that represents the fractional Ri with the power of 2 as the denominator
First computing means for computing Bi; when writing to the memory means, the data clock DCLK that determines the pixel unit of the original image data is given to the address counting means as a count pulse, and when reading from the memory means, the data clock DCLK I is changed by 1 in synchronism with the above, and when R <100, the up / down count means is instructed to up, and the data clock DCLK is given to the address count means as a count pulse, and Ji-Ji
_{When -1} = 2, the data clock DCLK is also given to the up / down count means, and when Ji-Ji- ₁ = 1, no count pulse is given to the up / down count means. When R ≧ 100, the up / down count means is instructed to down. Then, the data clock DCLK is applied to the address counting means, and Ji-Ji- ₁
= 1, the data clock DCLK is not given to the up / down counting means, and the data clock DCLK is also given to the up / down counting means when Ji-Ji _-1 = 0 to specify the sampling position for designating the read position x of the original image data. Means; and in synchronization with the data lock, input the original image data at the specified position x and one or more original image data adjacent thereto in bit units, and input the plurality of original image data to the data
An image data scaling processing apparatus comprising: a second arithmetic means configured by bit shift so as to compute scaled image data by a coefficient whose denominator is a power of 2 corresponding to Bi.