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JPS59111385A - Method of producing electronic circuit board - Google Patents

Method of producing electronic circuit board

Info

Publication number
JPS59111385A
JPS59111385A JP22141582A JP22141582A JPS59111385A JP S59111385 A JPS59111385 A JP S59111385A JP 22141582 A JP22141582 A JP 22141582A JP 22141582 A JP22141582 A JP 22141582A JP S59111385 A JPS59111385 A JP S59111385A
Authority
JP
Japan
Prior art keywords
electronic circuit
circuit
design information
ceramic substrate
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22141582A
Other languages
Japanese (ja)
Inventor
博正 山本
信太 三「きち」
竹島 明美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP22141582A priority Critical patent/JPS59111385A/en
Publication of JPS59111385A publication Critical patent/JPS59111385A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、産業用電子機器、一般民生用電子機器に用い
られる電子回路板の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing an electronic circuit board used in industrial electronic equipment and general consumer electronic equipment.

従来例の構成とその問題点 近年、電子機器の小形化、軽量化への要望が一段と高ま
シ、また多種小量生産の傾向も強まってきている。これ
らの要望に答えるため、機器を機能させる電子回路にお
いても、構成回路部品の高密度実装が行なわれている。
Conventional configurations and their problems In recent years, there has been a growing demand for smaller and lighter electronic devices, and there has also been a growing trend toward high-mix, low-volume production. In order to meet these demands, high-density packaging of constituent circuit components is being carried out even in the electronic circuits that make devices function.

代表的な従来の電子回路板の製造方法を説明すると、ま
ず電子回路を構成するだめの基板の製造工程があり、銅
箔張り積層板にフォトレジストを塗布し、これに所望の
導体回路パターンを有するフィルムを介して露光した後
、銅箔の不要な部分をエツチング処理して所望の導体回
路を形成する。
To explain the typical conventional manufacturing method for electronic circuit boards, there is first a manufacturing process for the blank board that makes up the electronic circuit. Photoresist is applied to a copper foil-covered laminate, and a desired conductor circuit pattern is formed on this. After exposing the copper foil to light through the film, unnecessary portions of the copper foil are etched to form a desired conductor circuit.

この導体回路を形成した基板上の所定の位置に、大きさ
が数叫角程度にチップ化された抵抗、コンデンサなどの
電子回路部品を配置し、半田付処理によって前記チップ
状電子回路部品の電気端子を導体回路に接続して電子回
路板とする。半田付処理には、溶融した半田の中にチッ
プ状電子回路部品を配置した基板を一定時間浸漬する半
田ディノプ工法や、導体回路を形成した基板に半田ペー
ストをスクリーン印刷し、その後チップ状の電子回路部
品を基板上に配置し、これを定められた温度で加熱する
半田リフロー工法は半田ディソプ工法に比べ高密度実装
ができる利点がある。
Electronic circuit components such as resistors and capacitors, which are chipped in size on the order of a few cryo angles, are placed at predetermined positions on the substrate on which the conductor circuit is formed, and the electronic circuit components are soldered by a soldering process. The terminals are connected to a conductor circuit to form an electronic circuit board. Soldering processes include the soldering process, in which a board on which chip-shaped electronic circuit components are placed is immersed in molten solder for a certain period of time, and the soldering process, in which solder paste is screen printed on a board on which a conductive circuit has been formed, and then the chip-shaped electronic circuit components are The solder reflow method, in which circuit components are placed on a board and heated at a predetermined temperature, has the advantage of allowing higher density mounting than the solder dispersion method.

上記従来の電子回路板の製造方法は、導体回路を形成す
るための露光用フィルムや半田リフロー工法を用いる場
合の半田ペーストを印刷するスクリーンなどネガパター
ンを用いる。従って、これらネガパターンを作る工程を
必要とし、また、回路パターンを変更するにはネガパタ
ーンから変更する必要があり、回路パターンの設計から
回路形成に至る作業性が著しく悪く、前述の電子機器の
多種小量生産の傾向に迅速に対応できないという問題が
あった。
The conventional electronic circuit board manufacturing method described above uses a negative pattern such as an exposure film for forming a conductor circuit or a screen for printing solder paste when using a solder reflow method. Therefore, a process of creating these negative patterns is required, and in order to change the circuit pattern, it is necessary to change from the negative pattern, and the workability from circuit pattern design to circuit formation is extremely poor, and the above-mentioned electronic equipment There was a problem in that it was not possible to respond quickly to the trend of high-mix, low-volume production.

発明の目的 本発明の目的は上記従来の欠点を除去し、ネガパターン
を用いることなく基板に直接的に導体回路の形成、及び
この導体回路と電子回路部品の電気端子との接続を行な
う電子回路板の製造方法を提供することにある。
Object of the Invention The object of the present invention is to eliminate the above-mentioned conventional drawbacks, and to provide an electronic circuit in which a conductor circuit is directly formed on a substrate without using a negative pattern, and the conductor circuit is connected to an electrical terminal of an electronic circuit component. The object of the present invention is to provide a method for manufacturing a board.

発明の構成 本発明の電子回路板の製造方法は、あらかじめ定めた回
路設計情報に基づいて、絶縁性基板上の所定の位置に電
子回路部品を配置した後、前記絶縁性基板上に所定の導
体回路を描画手段によって形成し、かつこの描画手段に
よって前記電子回路部品と前記導体回路とを電気的に接
続して、前記絶縁性基板上に直接電子回路を形成するも
のであり、描画手段によって導体回路の形成と、導体回
路と電子回路部品の電気端子との接続を行なうことによ
り、電子回路板が極めて短時間に製造できるものである
Structure of the Invention The method for manufacturing an electronic circuit board of the present invention includes arranging electronic circuit components at predetermined positions on an insulating substrate based on predetermined circuit design information, and then placing a predetermined conductor on the insulating substrate. A circuit is formed by a drawing means, and the electronic circuit component and the conductor circuit are electrically connected by the drawing means to directly form an electronic circuit on the insulating substrate. By forming the circuit and connecting the conductive circuit and the electrical terminals of the electronic circuit components, an electronic circuit board can be manufactured in an extremely short time.

実施例の説明 以下、本発明を実施例に基づいて説明する。Description of examples Hereinafter, the present invention will be explained based on examples.

第1図は本発明の一実施例を説明するためのブロックダ
イヤグラムであり、1は導体回路描画情報、電子回路部
品の種別、配置する位置などの回路設計情報を記憶し、
この回路設計情報に基づいて、後述する電子回路部品配
置手段2、描画手段3を制御する第1制御手段、2は絶
縁性基板上の所定の位置に電子回路部品を配置する電子
回路部品配置手段、3は導体回路を形成すると共に、こ
の導体回路と電子回路部品の電気端子とを接続する描画
手段である。
FIG. 1 is a block diagram for explaining one embodiment of the present invention, and 1 stores circuit design information such as conductor circuit drawing information, types of electronic circuit components, and placement positions;
Based on this circuit design information, first control means controls electronic circuit component placement means 2 and drawing means 3, which will be described later; 2 is electronic circuit component placement means for placing electronic circuit components at predetermined positions on an insulating substrate , 3 is a drawing means for forming a conductor circuit and connecting the conductor circuit to an electrical terminal of an electronic circuit component.

本発明に用いる絶縁性基板としては、アルシミ九ガラス
、はうろうなどのセラミック材料、あるいUフェノール
、エポキシ、ポリエステル、ホリイミドなどの樹脂材料
よシ成る基板を用いることができる。以下の説明ではセ
ラミック基板を代表例として説明する。
As the insulating substrate used in the present invention, a substrate made of a ceramic material such as aluminum oxide glass or porcelain, or a resin material such as Uphenol, epoxy, polyester, or polyimide can be used. In the following explanation, a ceramic substrate will be explained as a representative example.

本発明を第1図の実施例に従って説明すると、筐ずセラ
ミック基板を電子回路部品配置手段2に供給し、制御手
段1からの回路設計情報に従いセラミック基板を相対的
に移動させ、セラミック基板上の所定の位置に電子回路
部品を配置する。制御手段1としては例えばマイクロコ
ンピュータ。
The present invention will be described in accordance with the embodiment shown in FIG. Place electronic circuit components in predetermined positions. The control means 1 is, for example, a microcomputer.

ミニコンピユータなどを用いることができ、回路設計情
報の量に応じて選択する。電子回路部品配置手段2とし
、2は、例えは従来のチップマウンタに類するものを用
いることができる。
A minicomputer or the like can be used, and the selection is made depending on the amount of circuit design information. The electronic circuit component placement means 2 may be, for example, a device similar to a conventional chip mounter.

前記電子回路部品を配置したセラミック基板を描画手段
3に供給し、制御手段1からの回路設計情報に従いセラ
ミック基板を相対的に移動させ、電子回路部品を配置し
たセラミック基板上に描画ヘッドを用いて所定の導体回
路を形成する。さらに、上記描画ヘッドを用いてセラミ
ック基板上に配置した電子回路部品の電気端子と導体回
路とを接続する。
The ceramic substrate on which the electronic circuit components are arranged is supplied to the drawing means 3, the ceramic substrate is relatively moved according to the circuit design information from the control means 1, and the drawing head is used to place the ceramic substrate on which the electronic circuit components are arranged. A predetermined conductor circuit is formed. Further, the drawing head is used to connect the electrical terminals of the electronic circuit components arranged on the ceramic substrate to the conductive circuit.

描画ヘッドとしては、例えばインクジェット噴射記録ヘ
ッドを用いることができる。第2図に描画ヘッドの一例
を断面図で示す。同図において、4は描画ヘッドのベー
ス容器で、その−面にはダイヤフラム5が形成されてい
る。6は圧電素子であり駆動源10で駆動される。7は
吐出口、8は圧力室、9はパイプであり、圧力室8はベ
ース容器4とダイヤフラム5で気密に構成され、パイプ
9を介して導体回路を描画する塗料が満たされている。
As the drawing head, for example, an ink jet recording head can be used. FIG. 2 shows a cross-sectional view of an example of a drawing head. In the figure, reference numeral 4 denotes a base container of the drawing head, and a diaphragm 5 is formed on the negative side of the base container. A piezoelectric element 6 is driven by a drive source 10. 7 is a discharge port, 8 is a pressure chamber, and 9 is a pipe. The pressure chamber 8 is airtightly constituted by the base container 4 and the diaphragm 5, and is filled with paint for drawing a conductor circuit through the pipe 9.

上記描画ヘッドの動作を説明すると、圧電素子6に駆動
源10から電気的パルスを印加し、ダイヤフラム5が圧
力室8側に凸に変形すると、圧力室8の内容積が減じて
圧力が上昇し、吐出ロアより塗料が噴出する。ダイヤフ
ラム6が圧電素子6側に凸に変形すると、圧力室8の内
容積が増大して圧力が下が9、その結果、ツクイブ9を
介し塗料が補給される。
To explain the operation of the drawing head, when an electric pulse is applied to the piezoelectric element 6 from the drive source 10 and the diaphragm 5 deforms convexly toward the pressure chamber 8, the internal volume of the pressure chamber 8 decreases and the pressure increases. , paint is ejected from the discharge lower. When the diaphragm 6 deforms in a convex manner toward the piezoelectric element 6, the internal volume of the pressure chamber 8 increases and the pressure decreases.As a result, paint is replenished via the tube 9.

描画ヘッドによる導体回路の描画、及び電子回路部品の
電気端子と導体回路との接続についてさらに詳しく説明
する。第3図、第4図に上記描画と接続の動作を示す。
The drawing of a conductor circuit by the drawing head and the connection between the electrical terminal of the electronic circuit component and the conductor circuit will be described in more detail. FIGS. 3 and 4 show the drawing and connection operations described above.

11は第2図に示した描画ヘッド、12は例えば銀ペー
ストなどの導電性塗料、13は導電性塗料12の吐出に
よって形成された導体回路、14はセラミック基板、1
5はチップ状電子回路部品、16は電子回路部品16の
電気端子である。描画ヘッド11に電気的ノ(ルスを印
加すると導電性塗料12が吐出され、セラミック基板1
4の表面に付着する。同時に、回路設計情報に基づいて
セラミック基板14を描画ヘッド11に対し相対的に移
動させると、所定の)くターンの導体回路13が得られ
る。導体回路13の幅は主として吐出ロアの寸法、吐出
ロアとセラミック基板との距離によって定まるが、吐出
ロアとセラミック基板14との距離を大きくとると、導
体回路13の周辺部に、導体回路13とセラミック基板
子との境界が不明確になるにじみのような現象が生じ、
導体回路13において短絡が生じる場合がある。従って
、前記距離は5咽以下とするのが好ましい。
11 is the drawing head shown in FIG. 2; 12 is a conductive paint such as silver paste; 13 is a conductor circuit formed by discharging the conductive paint 12; 14 is a ceramic substrate;
5 is a chip-shaped electronic circuit component, and 16 is an electrical terminal of the electronic circuit component 16. When an electric current is applied to the drawing head 11, the conductive paint 12 is discharged and the ceramic substrate 1 is
It adheres to the surface of 4. At the same time, by moving the ceramic substrate 14 relative to the drawing head 11 based on the circuit design information, a conductor circuit 13 with a predetermined number of turns is obtained. The width of the conductor circuit 13 is mainly determined by the dimensions of the discharge lower and the distance between the discharge lower and the ceramic substrate, but if the distance between the discharge lower and the ceramic substrate 14 is large, the conductor circuit 13 and A bleed-like phenomenon occurs where the boundary with the ceramic substrate becomes unclear.
A short circuit may occur in the conductor circuit 13. Therefore, it is preferable that the distance is 5 or less.

導電性塗料12をセラミック基板14から電子回路部品
15の電気端子16まで連続的に吐出すると、第4図に
示したように導体回路13と電気端子16とを電気的に
接続することができる。電気的接続をより確実にするた
め、接続部近傍でのセラミック基板14と描画ヘッド1
1との相対速度を導体回路13の描画時のμ〜’Ioに
するのが好ましい。また、第5図に示すように接続部近
傍での導電性塗料12の吐出方向とセラミック基板7と
のなす角度を90度よシ小さく(好ましくは46度近傍
に〕すると、さらに確実な接続が得られる。
When the conductive paint 12 is continuously discharged from the ceramic substrate 14 to the electrical terminals 16 of the electronic circuit component 15, the conductor circuit 13 and the electrical terminals 16 can be electrically connected as shown in FIG. In order to make the electrical connection more reliable, the ceramic substrate 14 and the drawing head 1 are connected near the connection part.
It is preferable that the relative velocity with respect to 1 is μ to 'Io at the time of drawing the conductor circuit 13. Further, as shown in FIG. 5, if the angle between the discharge direction of the conductive paint 12 and the ceramic substrate 7 near the connection part is made smaller than 90 degrees (preferably around 46 degrees), a more reliable connection can be achieved. can get.

なお、導電性塗料を硬化させるためには、各導電性塗料
に応じた温度、時間で熱処理を行なうことが必要であり
、本発明においてもこの熱処理工程は当然含むものであ
る。
In order to cure the conductive paint, it is necessary to perform heat treatment at a temperature and time depending on each conductive paint, and the present invention naturally includes this heat treatment step.

以上述べたように、本実施例では電子回路部品を配置し
た絶縁性基板上に、電子回路部品の電気端子と接続した
導体回路をインクジェット噴射記録ヘッドで直接的に形
成することにより、電子回路板の製造工数の大幅な低減
を実現している。
As described above, in this example, an electronic circuit board is formed by directly forming a conductive circuit connected to the electrical terminal of the electronic circuit part on an insulating substrate on which the electronic circuit part is arranged, using an inkjet jet recording head. This has resulted in a significant reduction in manufacturing man-hours.

第6図は本発明の他の実施例を説明するためのブロック
ダイヤグラムであり、第1制御手段1、電子回路部品配
置手段2、描画手段3はそれぞれ前記実施例の制御手段
、電子回路部品配置手段、描画手段と同一の機能をもつ
ものである。17は絶縁性基板であるセラミック基板上
に配置した電子回路部品の実際の配置位置を検出する配
置位置検出手段、18は回路設計情報修正手段、19は
第2制御手段である。
FIG. 6 is a block diagram for explaining another embodiment of the present invention, in which the first control means 1, electronic circuit component arrangement means 2, and drawing means 3 are the control means and electronic circuit component arrangement means of the above embodiment, respectively. It has the same function as the means and drawing means. Reference numeral 17 designates placement position detection means for detecting the actual placement positions of electronic circuit components placed on a ceramic substrate, which is an insulating substrate; 18, circuit design information correction means; and 19, second control means.

本実施例を第6図に従って説明すると、まずセラミック
基板を電子回路部品配置手段2に供給し、第1制御手段
1からの回路設計情報に従いセラミック基板を相対的に
移動させ、セラミック基板上の所定の位置に電子回路部
品を配置する。このセラミック基板を配置位置検出手段
1γに供給し、電子回路部品の実際の配置位置を検出す
る。検出した実際の配置位置情報は回路設計情報修正手
段18に転送される。
This embodiment will be explained according to FIG. 6. First, a ceramic substrate is supplied to the electronic circuit component placement means 2, and the ceramic substrate is relatively moved according to the circuit design information from the first control means 1. Place the electronic circuit components at the position. This ceramic substrate is supplied to the arrangement position detecting means 1γ, and the actual arrangement position of the electronic circuit component is detected. The detected actual placement position information is transferred to the circuit design information modification means 18.

一方、第1制御手段1の回路設計情報は回路設計情報修
正手段18に転送され、上記電子回路部品の実際の配置
位置情報で修正された後、第2制御手段19に転送され
る。
On the other hand, the circuit design information of the first control means 1 is transferred to the circuit design information correction means 18, and after being corrected with information on the actual placement positions of the electronic circuit components, it is transferred to the second control means 19.

ここで、回路設計情報の修正について説明する。Here, correction of circuit design information will be explained.

本実施例における回路設計情報の修正とは、例えば電子
回路部品配置手段での配置位置の誤差や。
In this embodiment, the correction of circuit design information refers to, for example, errors in placement positions in electronic circuit component placement means.

振動等によ□る電子回路部品の位置ずれ等、比較的小さ
な範囲での位置ずれに対し、電子回路部品の電気端子と
導体回路とが確実に接続できるように電子回路部品の電
気端子付近の導体回路描画情報を修正することを意味す
る。従って、例えば電子回路部品の一部を除去するもし
くは加えるというような修正は、第1制御手段の回路設
計情報を変更する。
In order to ensure that the electrical terminals of electronic circuit components and conductor circuits can be reliably connected against misalignment of electronic circuit components in a relatively small range, such as misalignment of electronic circuit components due to vibration, etc., This means modifying the conductor circuit drawing information. Therefore, a modification such as removing or adding a part of an electronic circuit component changes the circuit design information of the first control means.

前記電子回路部品の実際の配置位置を検出されたセラミ
ック基板を描画手段3に供給し、第2制御手段からの修
正した回路設計情報に従いセラミック基板を相対的に移
動させ、電子回路部品を配置したセラミック基板上に描
画ヘッドを用いて導体回路を形成する。さらに、上記描
画ヘッドを用いてセラミック基板上に配置した電子回路
部品の電気端子と導体回路とを接続する。
The ceramic substrate on which the actual placement position of the electronic circuit component has been detected is supplied to the drawing means 3, and the ceramic substrate is relatively moved according to the corrected circuit design information from the second control means to arrange the electronic circuit component. A conductor circuit is formed on a ceramic substrate using a drawing head. Further, the drawing head is used to connect the electrical terminals of the electronic circuit components arranged on the ceramic substrate to the conductive circuit.

配置位置検出手段17の一例を第7図にブロックダイヤ
グラムで示す。2oはイメージセンサカメラ、21は2
値化手段、22ij特徴抽出手段、23は記憶手段、1
4はセラミック基板を示す。
An example of the arrangement position detecting means 17 is shown in a block diagram in FIG. 2o is an image sensor camera, 21 is 2
Value conversion means, 22ij feature extraction means, 23 storage means, 1
4 indicates a ceramic substrate.

電子回路部品(図示せず)を配置したセラミック基板1
4の表面をイメージセンサカメラ20で画像情報として
とらえ、この画像情報信号を2値化手段21によジ°゛
1”と0″の信号に変換する。
Ceramic substrate 1 on which electronic circuit components (not shown) are arranged
The surface of 4 is captured as image information by the image sensor camera 20, and this image information signal is converted into signals of ``1'' and 0'' by the binarization means 21.

2値化した信号から特徴抽出手段22でセラミック基板
14と電子回路部品との境界を抽出し、この境界を平面
座表値に変換して記憶手段23に格納する。
The feature extraction means 22 extracts the boundary between the ceramic substrate 14 and the electronic circuit component from the binarized signal, converts this boundary into a plane coordinate value, and stores it in the storage means 23.

なお、第6図では第1制御手段11回路設計情報修正手
段18、第2制御手段19を個々に示したが、これらは
第1制御手段と一体化できる。また第7図の2値化手段
21、特徴抽出手段22、記憶手段23も第6図の第1
制御手段1と一体化できる。
Although the first control means 11, circuit design information modification means 18, and second control means 19 are shown individually in FIG. 6, they can be integrated with the first control means. Furthermore, the binarization means 21, feature extraction means 22, and storage means 23 in FIG.
It can be integrated with the control means 1.

以上述べたように、本実施例では配置位置検出手段を設
けることにより、電子回路部品の配置位置のずれを修正
して導体回路を抽画でき、回路基板の製造歩留の向上を
実現している。
As described above, by providing the placement position detection means in this embodiment, it is possible to correct deviations in the placement positions of electronic circuit components and draw conductor circuits, thereby improving the manufacturing yield of circuit boards. There is.

発明の効果 以上の説明から明らかなように、本発明は電子回路部品
を配置した絶縁性基板上に直接導体回路を形成し、同時
に電子回路部品の電気端子と導体回路との接続を行なう
ものであり、電子回路板が極めて短時間に製造でき、ま
た、多種小量生産という近年の電子機器の傾向に十分対
応できるものである。
Effects of the Invention As is clear from the above explanation, the present invention forms a conductor circuit directly on an insulating substrate on which electronic circuit components are arranged, and at the same time connects the electrical terminals of the electronic circuit components and the conductor circuit. This allows electronic circuit boards to be manufactured in an extremely short time, and is fully compatible with the recent trend in electronic equipment to produce a wide variety of products in small quantities.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロックダイヤグラム
、第2図は本発明の一実施例に用いる描画ヘッドの断面
図、第3図〜第5図は本発明の一実施例における描画手
段の動作を説明する説明図、第6図は本胤明の他の実施
例を示すブロックダイヤグラム、第7図は本発明の配置
位置検出手段の一例を示す構成図である。 1・・・・・・第1制御手段、2・・・・・・電子回路
部品配置手段、3・・・・・・描画手段、11・・・・
・・描画ヘッド。 17・・・・・・配置位置検出手段、18・・・・・・
回路設計情報修正手段、19・・・・・・第2制御手段
、20・・・・・・イメージセンサカメラ、21・・・
・・・2値化手段、22・・・・・・特徴抽出手段、2
3・・・・・・記憶手段。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 第3図 第4図 4 第6図 /’/         J 第7図
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a sectional view of a drawing head used in an embodiment of the invention, and FIGS. 3 to 5 are drawing means in an embodiment of the invention. FIG. 6 is a block diagram showing another embodiment of the present invention, and FIG. 7 is a configuration diagram showing an example of the arrangement position detecting means of the present invention. 1...First control means, 2...Electronic circuit component arrangement means, 3...Drawing means, 11...
...Drawing head. 17... Arrangement position detection means, 18...
Circuit design information correction means, 19... second control means, 20... image sensor camera, 21...
... Binarization means, 22 ... Feature extraction means, 2
3...Memorization means. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4 Figure 4 Figure 6/'/J Figure 7

Claims (1)

【特許請求の範囲】[Claims] (1)あらかじめ定めた回路設計情報に基づいて、絶縁
性基板上の所定の位置に電子回路部品を配置した後、前
記絶縁性基板上に所定の形状の導体回路を描画手段によ
って形成し、かつ、この描画手段によって前記電子回路
部品と前記導体回路とを電気的に接続することを特徴と
する電子回路板の製造方法。 @)絶縁性基板上の所定の位置に配置された電子回路部
品の実配置位置を検出し、前記回路設計情報を前記検出
した実配置位置情報で修正し。 この修正した回路設計情報に基づいて前記絶縁性基板上
に導体回路を形成することを特徴とする特許請求の範囲
第(1)項記載の電子回路板の製造方法。
(1) After arranging electronic circuit components at predetermined positions on an insulating substrate based on predetermined circuit design information, forming a conductive circuit in a predetermined shape on the insulating substrate by a drawing means, and . A method of manufacturing an electronic circuit board, characterized in that the electronic circuit component and the conductor circuit are electrically connected by the drawing means. @) Detecting the actual placement position of the electronic circuit component placed at a predetermined position on the insulating substrate, and correcting the circuit design information with the detected actual placement position information. The method of manufacturing an electronic circuit board according to claim 1, wherein a conductive circuit is formed on the insulating substrate based on the corrected circuit design information.
JP22141582A 1982-12-16 1982-12-16 Method of producing electronic circuit board Pending JPS59111385A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22141582A JPS59111385A (en) 1982-12-16 1982-12-16 Method of producing electronic circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22141582A JPS59111385A (en) 1982-12-16 1982-12-16 Method of producing electronic circuit board

Publications (1)

Publication Number Publication Date
JPS59111385A true JPS59111385A (en) 1984-06-27

Family

ID=16766376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22141582A Pending JPS59111385A (en) 1982-12-16 1982-12-16 Method of producing electronic circuit board

Country Status (1)

Country Link
JP (1) JPS59111385A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63289895A (en) * 1987-05-21 1988-11-28 Matsushita Electric Ind Co Ltd Formation of thick-film circuit
JPH02158032A (en) * 1988-12-09 1990-06-18 Hakusan Seisakusho:Kk Method of forming trigger line of gas-containing discharge tube
US7952888B2 (en) 2006-05-09 2011-05-31 Canon Kabushiki Kaisha Wiring module
US9232300B2 (en) 2013-03-15 2016-01-05 Yamaha Corporation Bass reflex port and tubular body

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63289895A (en) * 1987-05-21 1988-11-28 Matsushita Electric Ind Co Ltd Formation of thick-film circuit
JPH02158032A (en) * 1988-12-09 1990-06-18 Hakusan Seisakusho:Kk Method of forming trigger line of gas-containing discharge tube
US7952888B2 (en) 2006-05-09 2011-05-31 Canon Kabushiki Kaisha Wiring module
US9232300B2 (en) 2013-03-15 2016-01-05 Yamaha Corporation Bass reflex port and tubular body

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