JPH01268095A - Film circuit substrate and manufacture of circuit device using same - Google Patents
Film circuit substrate and manufacture of circuit device using sameInfo
- Publication number
- JPH01268095A JPH01268095A JP9552188A JP9552188A JPH01268095A JP H01268095 A JPH01268095 A JP H01268095A JP 9552188 A JP9552188 A JP 9552188A JP 9552188 A JP9552188 A JP 9552188A JP H01268095 A JPH01268095 A JP H01268095A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- circuit board
- row
- terminal electrode
- electrode patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 title description 4
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000012528 membrane Substances 0.000 claims description 3
- 230000005855 radiation Effects 0.000 claims 1
- 239000010408 film Substances 0.000 description 7
- 238000005476 soldering Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は膜回路基板及び該模回ｗ！ｒ基板金用いた回路
装置の製造方法に関し、詳しくはハイブリツドＩｃや面
実ｆ７を型プリント基板への部品半田Ｕ′けに係９、特
に小形パッケージＩＣ等の多端子面実装型部品の半田付
は接続に好適な基板の電憾端子パターン形状及び半田ペ
ースト印刷形状に関する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a membrane circuit board and its simulation w! Regarding the manufacturing method of circuit devices using r-substrate metal, for details, refer to the soldering of components U' to hybrid IC and surface area F7 type printed circuit boards9, especially the soldering of multi-terminal surface mount type components such as small package ICs. The present invention relates to the shape of an electric terminal pattern and the shape of printed solder paste on a board suitable for connection.
面実装型の電子部品の半田付接続法として、半田ベース
トリフａ一方法が広り実力されているが、半田付し交際
の半田付状況を良好ならしめるためにはフィレットを充
分高（する必要がめり、従来、特開昭６０−５２０９２
号にボすように半田ｔｔ九分に供給するため、半田
ペーストパターンは電極端子パターンを半田ペーストに
よって８おい隠すように広くしていた。As a soldering connection method for surface-mounted electronic components, the solder base trifling method is widely used and proven, but the fillet must be set at a sufficiently high height in order to achieve a good soldering condition during soldering. Gameri, conventional, JP-A-60-52092
In order to supply solder tt 9 times as wide as the number, the solder paste pattern was widened so that the electrode terminal pattern was covered by 8 times the solder paste.
上記従来技術によれば、面実装型部品のリードを接続す
るべき電極端子パターンは、その上に印刷した半田ペー
ストによって隠蔽される之め目標が消滅するので、上記
面実装型部品を搭載した場合に、そのｉａ位置が上記電
極端子パターンからはすれて、続いて加熱９７ａ−工程
において半田を浴融後冷却固化した時に、上記面実装４
部品のリードが、所定の！極端子パターンから離れてし
まって、非接続となったシ、所定の１極端子パターン以
外の１ａｃ極端子パターンに誤接続され友ジ、１４接Ｉ
Ｉｃ極端子パタ一ン間に位置して、この隣接電極端子パ
ターンを短絡接続する不良を発生する問題がめった。According to the above conventional technology, the electrode terminal pattern to which the lead of the surface mount type component is to be connected is hidden by the solder paste printed on it, so that the target disappears, so when the above surface mount type component is mounted. Then, when the ia position is separated from the electrode terminal pattern and the solder is melted in a bath and then cooled and solidified in the heating step 97a, the surface mount 4
Part leads are in place! 1ac terminal terminal pattern other than the predetermined 1ac terminal pattern, and 14 terminal terminal pattern is disconnected.
A problem has frequently arisen in which a defect occurs where the Ic electrode terminal pattern is located between two adjacent electrode terminal patterns and the adjacent electrode terminal patterns are short-circuited.
本発明の目的は、上記問題点発生を排除するべく、牛田
ペーストヲ印刷しても電極端子パターンの位置を示す目
標を残存させることにるる。SUMMARY OF THE INVENTION In order to eliminate the above-mentioned problems, it is an object of the present invention to allow a target indicating the position of an electrode terminal pattern to remain even when Ushida paste is printed.
上記目的は、列状に連なった電極端子パターンの形状を
、上記列と直交する方向に大きく設けることにより、半
田ペーストを印刷し交際に上記の大きくした部分が、半
田ペーストから露出することによシ達成される。The above purpose is to make the shape of the electrode terminal pattern connected in a row large in the direction perpendicular to the row, so that when solder paste is printed, the enlarged part is exposed from the solder paste. is achieved.
以下、本発明の一実施例を第１図及び第２図により説明
する。第１図は本発明の一実施例の厚膜回路基板の要部
平面図、第２図は第１図の厚膜回路基板を使用した回路
装置勿形成する中途工程の第１図に対応した部分の平面
図である。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a plan view of essential parts of a thick film circuit board according to an embodiment of the present invention, and FIG. 2 corresponds to FIG. 1 showing an intermediate process of forming a circuit device using the thick film circuit board of FIG. 1. FIG.
同図において、絶縁セラミック基板上にＡｆＰｄを主成
分とする導電ペースト及び凡ｕＯ，を生成分とする抵抗
ペーストを順次印桐滉成して、ＩＥ億配線１と列状に連
らなった端子′ＩＩＬ極２．該列と直交方向に形状と拡
大しｆｃ拡大端子を極２°及び抵抗３を形成して厚膜回
路ｉ板を形成した後、この厚膜回１！＆基板の端子電極
２１に蔽い隠すように充分広く、また拡大端子電極２°
の拡大部分が露出するように半田ペースト４ｔ−印刷し
、更に上記露出部分き目標（目視）にしてリード端子５
を具備する部品６ｆｃ搭載し位置照合Ａ４！ｌｋシた後
、赤外ＭＡ加熱万式及び温風カロ熱方式等の刀Ｕ熱手段
によジ牛田ベーストをり７０−して半田付接続して形成
するものである。In the same figure, a conductive paste mainly composed of AfPd and a resistive paste mainly composed of O2 are sequentially deposited on an insulating ceramic substrate to form terminals connected in a row with IE wires 1. 'IIL pole 2. After expanding the shape in the direction perpendicular to the column and forming the fc enlarged terminal with a pole of 2° and a resistor 3 to form a thick film circuit I board, this thick film circuit 1! & Wide enough to cover and hide the terminal electrode 21 of the board, and the enlarged terminal electrode 2°
4T of solder paste is printed so that the enlarged part of
Equipped with 6fc parts and position verification A4! After heating, the base plate is connected by soldering using heat means such as an infrared MA heating method or a hot air heating method.
本実施例によれば、部品６のリード端子５ｔ−１回ｗ！
ｒ基板の拡大端子を極２°に対して高ｄ度に位置合わせ
することができて、他のリード端子と端子′１極パター
ンの相対位置を予じめ設定しておくことにより、ｆＡ誤
接続び不接続、短絡接続等の不良を回避することができ
る。According to this embodiment, lead terminal 5t of component 6-1 time w!
It is possible to align the enlarged terminal of the r board at a high degree of d with respect to the pole 2 degrees, and by setting the relative position of the other lead terminals and the terminal '1 pole pattern in advance, fA errors can be avoided. It is possible to avoid defects such as connection/disconnection and short-circuit connection.
本発明によれば、端子ｘｍ形状を全体的でなく部分的に
拡大することにより、目視ｔ−含めた位置認識手段と、
部品位置方向移動手段とを適宜活用することによって、
高精度高信頼性の面実装接続を提供することができるの
で、集積密度の看るしい低下を招くことなく低価格で高
信頼性の回ＴＲ１ｒ装置ｔを提供できる効果がある。According to the present invention, by enlarging the terminal xm shape not entirely but partially, the position recognition means including the visual inspection t-
By appropriately utilizing the component position direction moving means,
Since it is possible to provide surface-mounted connections with high precision and high reliability, it is possible to provide a highly reliable circuit TR1r device t at a low cost without causing a noticeable decrease in integration density.
また実施例においては、電極材料としてＡｆＰｄを主成
分に用いたが、その他の例えばｋｆＰｔ系、Ｃｕ系材料
であっても（’Ｉら差しつかえなく、上記効果を得るこ
とができる。更に上記の厚ｇ４板ではなり、蒸着エツチ
ング手段等にて形成する薄膜基板でもよく、またＣｕ箔
、 Ｃｕめつき膜を利用したプリント基板でも同様の効
果を得ることができる。Furthermore, in the examples, AfPd was used as the main component as the electrode material, but other materials such as kfPt-based and Cu-based materials ('I) can also be used to obtain the above effects. A thin film substrate formed by vapor deposition and etching means may be used instead of a G4 thick plate, and the same effect can be obtained with a printed circuit board using Cu foil or Cu plating film.
第１図は本発明の一実施例の厚膜回路基板の要部平面図
、第２図は第１図の厚膜回路基板を使用した回路装置の
中途工程における第１図に対応した部分の平面図である
。
１・・・電極配線、２・・・端子電極、２°・・・拡大
端子電極、３・・・抵抗、４・・・半田ペースト、５・
・・部品リード端子、６・・・部品。FIG. 1 is a plan view of essential parts of a thick film circuit board according to an embodiment of the present invention, and FIG. 2 is a partial plan view of a circuit device using the thick film circuit board of FIG. FIG. DESCRIPTION OF SYMBOLS 1... Electrode wiring, 2... Terminal electrode, 2°... Expanded terminal electrode, 3... Resistor, 4... Solder paste, 5...
...Component lead terminal, 6...Part.
Claims (3)
なる膜回路基板において、上記複数の端子電極パターン
のうちの一つ以上は他の端子電極パターンよりも列と直
交する方向に寸法が大きいことを特徴とする膜回路基板
。1. In a film circuit board comprising a plurality of terminal battery patterns having substantially the same shape arranged in a row, one or more of the plurality of terminal electrode patterns has a larger dimension in a direction perpendicular to the row than the other terminal electrode patterns. A membrane circuit board featuring:
れてなることを特徴とする請求項１記載の膜回路基板。2. 2. The membrane circuit board according to claim 1, wherein the larger terminal electrode pattern is arranged at the end of the row.
なり、該複数の端子電極パターンのうちの一つ以上は他
の端子電極パターンよりも列と直交する方向に寸法が大
きい膜回路基板を用いた回路装置の製造方法であって、
該膜回路基板に半田ペーストを印刷する工程と、面実装
型多端子部品及びその他部品を搭載する工程と、赤外線
輻射等の加熱手段によるリフロー工程とを具備すること
を特徴とする回路装置製造方法。3. A film circuit board is used in which a plurality of terminal electrode patterns having substantially the same shape are arranged in a row, and one or more of the plurality of terminal electrode patterns has a larger dimension in a direction perpendicular to the row than other terminal electrode patterns. A method for manufacturing a circuit device comprising:
A method for manufacturing a circuit device, comprising the steps of printing solder paste on the film circuit board, mounting surface-mounted multi-terminal components and other components, and reflowing using heating means such as infrared radiation. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9552188A JPH01268095A (en) | 1988-04-20 | 1988-04-20 | Film circuit substrate and manufacture of circuit device using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9552188A JPH01268095A (en) | 1988-04-20 | 1988-04-20 | Film circuit substrate and manufacture of circuit device using same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01268095A true JPH01268095A (en) | 1989-10-25 |
Family
ID=14139868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9552188A Pending JPH01268095A (en) | 1988-04-20 | 1988-04-20 | Film circuit substrate and manufacture of circuit device using same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01268095A (en) |
-
1988
- 1988-04-20 JP JP9552188A patent/JPH01268095A/en active Pending
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