JPH0231794Y2 - - Google Patents
Info
- Publication number
- JPH0231794Y2 JPH0231794Y2 JP1984089134U JP8913484U JPH0231794Y2 JP H0231794 Y2 JPH0231794 Y2 JP H0231794Y2 JP 1984089134 U JP1984089134 U JP 1984089134U JP 8913484 U JP8913484 U JP 8913484U JP H0231794 Y2 JPH0231794 Y2 JP H0231794Y2
- Authority
- JP
- Japan
- Prior art keywords
- substrates
- electronic components
- ceramic
- ceramic substrates
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 37
- 239000000919 ceramic Substances 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims 1
- 230000010354 integration Effects 0.000 description 9
- 238000004191 hydrophobic interaction chromatography Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000002075 main ingredient Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Landscapes
- Combinations Of Printed Boards (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案は、集積度を向上させたハイブリツド集
積回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a hybrid integrated circuit with an improved degree of integration.
セラミツク基板に厚膜印刷技術で配線パターン
と抵抗を印刷し、印刷できないトランジスタ、コ
ンデンサ、半導体集積回路等の電子部品は半田付
けで搭載する形式のハイブリツド集積回路(以
下、HICと呼ぶ)は、1つの電子部品として電子
機器の中に実装される。車載用機器のように小型
なものでは実装スペースも狭いため、より集積度
の高いHICが要求される。
Hybrid integrated circuits (hereinafter referred to as HICs), in which wiring patterns and resistors are printed on a ceramic substrate using thick-film printing technology, and electronic components such as transistors, capacitors, and semiconductor integrated circuits that cannot be printed are mounted by soldering, are: It is mounted in electronic equipment as one electronic component. Since the mounting space for small devices such as in-vehicle equipment is limited, HICs with a higher degree of integration are required.
第3図は従来のシングルインライン(SIL)型
HICの3面図、第4図はデユアルインライン
(DIL)型HICの側面図である。図中、1はセラ
ミツク基板で、その一面には厚膜印刷技術で配線
パターンや抵抗(いずれも図示せず)が印刷され
ている。2はトランジスタ、半導体集積回路等の
電子部品で、基板1の配線パターンが形成された
面にリフロー半田付けで固定されている。3は外
部端子で、基板1の側部に半田4で固定され、所
要とする導電パターンに接続される。この外部端
子3を基板1の片側だけに設けるHICが第3図の
SIL型で、両側に設けるHICが第4図のDIL型で
ある。SIL型は基板1を直立させて図示せぬプリ
ント配線板に実装し、またDIL型は基板1を水平
にして実装する。 Figure 3 shows the conventional single-in-line (SIL) type
Figure 4 is a side view of the dual-in-line (DIL) type HIC. In the figure, 1 is a ceramic substrate, on one side of which wiring patterns and resistors (none of which are shown) are printed using thick film printing technology. Reference numeral 2 denotes electronic components such as transistors and semiconductor integrated circuits, which are fixed by reflow soldering to the surface of the substrate 1 on which the wiring pattern is formed. Reference numeral 3 denotes an external terminal, which is fixed to the side of the substrate 1 with solder 4 and connected to a required conductive pattern. The HIC in which this external terminal 3 is provided only on one side of the board 1 is shown in Figure 3.
The HIC installed on both sides of the SIL type is the DIL type shown in Figure 4. The SIL type is mounted on a printed wiring board (not shown) with the board 1 standing upright, and the DIL type is mounted with the board 1 horizontal.
この種のHICへの搭載素子数は使用するセラミ
ツク基板の面積によつて制限され、集積度には一
定の限界がある。そこで1枚のセラミツク基板の
表裏面を使用して集積度を倍化する試みがなされ
ている。しかし、このためには表裏面の導電パタ
ーンを一部で接続するためのスルーホール製造技
術や、両面に同時に電子部品を半田付けするため
に裏面側の電子部品を予め基板面に接着剤で仮止
めしたり、さらには高温の不活性ガス中でリフロ
ー用半田を加熱、固化するというベーパーフロー
方式を採用する必要があり、製造工程が複雑且つ
高度化する難点があり、またそのことに伴ない不
良品の発生確率が高まる欠点がある。 The number of elements mounted on this type of HIC is limited by the area of the ceramic substrate used, and there is a certain limit to the degree of integration. Therefore, attempts have been made to double the degree of integration by using the front and back surfaces of a single ceramic substrate. However, for this purpose, through-hole manufacturing technology is needed to partially connect the conductive patterns on the front and back sides, and in order to solder electronic components on both sides at the same time, the electronic components on the back side are temporarily attached to the board surface with adhesive in advance. It is necessary to use a vapor flow method in which reflow solder is heated and solidified in a high-temperature inert gas, making the manufacturing process complicated and sophisticated. This has the disadvantage of increasing the probability of producing defective products.
そこで、集積度を簡単な構成で向上させるため
の構成として実開昭55−84980号公報に示される
ように、2枚の基板の各一面に部品を半田付け
し、他面同士を接着して一体化したものが知られ
ている。 Therefore, as shown in Japanese Utility Model Application Laid-Open No. 55-84980, as a structure for improving the degree of integration with a simple structure, components are soldered to one side of each of two boards and the other sides are bonded together. It is known that it is integrated.
ところがかかる先行技術では両基板間の電気的
接続はスルーホールにより行われているため、こ
れをセラミツク基板に適用した場合スルーホール
製造技術を採用する必要があるため前述した製造
工程の複雑化、高度化並びに不良品の発生確率の
増大という問題点を解決することはできない。
However, in such prior art, the electrical connection between the two boards is made through through holes, so when this is applied to a ceramic board, it is necessary to employ through hole manufacturing technology, which increases the complexity and sophistication of the manufacturing process as described above. However, it is not possible to solve the problems of increasing the probability of defective products.
本考案は2枚のセラミツク基板を接着するとい
う簡単な工程で1つのHICの集積度を高めると共
に、2枚のセラミツク基板間の電気的接続を簡単
な構成で実現しようとするものである。 The present invention aims to increase the degree of integration of a single HIC through the simple process of bonding two ceramic substrates together, and to realize electrical connection between the two ceramic substrates with a simple configuration.
本考案のハイブリツド集積回路は、2枚のセラ
ミツク基板の各一面に配線パターンを形成して必
要な電子部品を半田付けし、且つ該2枚のセラミ
ツク基板の他面同士を接着して一体化し、さらに
両基板の端部を挟むように両基板の配線パターン
に共通接続される外部端子を設けてなることを特
徴とするものである。
The hybrid integrated circuit of the present invention is produced by forming a wiring pattern on each side of two ceramic substrates, soldering the necessary electronic components, and bonding the other surfaces of the two ceramic substrates together to integrate them. Furthermore, an external terminal is provided which is commonly connected to the wiring patterns of both substrates so as to sandwich the ends of both substrates.
予め各セラミツク基板の一面に導電パターンを
形成してその面に電子部品を半田付けしておき、
かかる基板を2枚、その未使用面同士を接着して
1つのHICを製造する技術は、単に接着工程を追
加するのみであるから製造は容易であり、また不
良品発生確率も低い。
A conductive pattern is formed on one surface of each ceramic substrate in advance, and electronic components are soldered to that surface.
The technique of manufacturing one HIC by bonding the unused surfaces of two such substrates together is easy to manufacture because it simply requires an additional bonding process, and the probability of producing defective products is low.
しかも、外部端子は両基板の配線パターンに共
通接続されるので、両基板間の電気的接続は外部
端子を基板に取付けることで同時に達成される。 Furthermore, since the external terminals are commonly connected to the wiring patterns of both substrates, electrical connection between both substrates can be achieved simultaneously by attaching the external terminals to the substrates.
以下、図面を参照しながら本考案の実施例を説
明する。
Embodiments of the present invention will be described below with reference to the drawings.
第1図は本考案の一実施例を示す製造工程順の
説明図で、1,1′は2枚の独立したセラミツク
基板、2,2′はそれらの導電パターン形成面に
リフロー半田付けで搭載された電子部品、3は外
部端子、4は半田である。aはセラミツク基板
1,1′に電子部品2,2′を搭載して、互いに電
子部品を搭載していない未使用面を対向させた状
態である。この状態から両未使用面相互間を接着
剤で接着し、同図bのように2枚の基板1,1′
を一体化する。このとき使用する接着剤は例えば
エポキシ系樹脂を主剤とする高熱伝導性接着剤
(商品名ラムダイト:電気化学工業)である。b
のように基板1,1′が一体化されてしまうと、
それは1枚のセラミツク基板の両面に導電パター
ンを形成し、且つそこに電子部品を搭載したもの
と同じ集積度になる。厚み方向に見ても、セラミ
ツク基板が1枚増加するとしても、標準厚みの場
合0.635mmの増加に過ぎず、またこの半分の厚み
のものを使用すれば全く増加しないで済む。この
ように接着した後に、両基板1,1′の端部を挟
む形で端子3を付け、半田付けする。cおよびd
はSIL型の正面図および端面図であり、またeは
DIL型の側面図である。このとき端子3は基板
1,1′のいずれか一方の導電パターンに接続さ
れる場合と、スルーホールのように両基板の導電
パターン間を短絡する場合とがある。 Figure 1 is an explanatory diagram of the manufacturing process order showing one embodiment of the present invention, where 1 and 1' are two independent ceramic substrates, and 2 and 2' are mounted on their conductive patterned surfaces by reflow soldering. 3 is an external terminal, and 4 is solder. A shows a state in which electronic components 2 and 2' are mounted on ceramic substrates 1 and 1', with the unused surfaces on which no electronic components are mounted facing each other. From this state, the two unused surfaces are bonded with adhesive, and the two substrates 1 and 1' are bonded together as shown in Figure b.
to integrate. The adhesive used at this time is, for example, a highly thermally conductive adhesive (trade name: Lambdite, manufactured by Denki Kagaku Kogyo) containing an epoxy resin as its main ingredient. b
If the substrates 1 and 1' are integrated as in
It has the same degree of integration as a single ceramic substrate with conductive patterns formed on both sides and electronic components mounted thereon. In terms of thickness, even if the number of ceramic substrates increases by one, the increase is only 0.635 mm if the thickness is standard, and if one with half this thickness is used, there will be no increase at all. After bonding in this manner, terminals 3 are attached and soldered to sandwich the ends of both substrates 1 and 1'. c and d
are the front view and end view of the SIL type, and e is the front view and end view of the SIL type.
FIG. 3 is a side view of the DIL type. At this time, the terminal 3 may be connected to a conductive pattern on one of the substrates 1, 1', or may be connected to a conductive pattern on both substrates such as a through hole.
第2図a〜cは本考案の他の実施例を示す構成
図で、いずれもセラミツク基板1,1′の間に銅、
アルミニウム等の放熱板5を介在させた点が第1
図と異なる。第2図aおよびbはSIL型で、aは
放熱板5の上端を折曲して機器上蓋に伝熱するも
の、bは放熱板5にネジ穴6を設けて機器側壁に
ネジ止め、伝熱するものである。またcはDIL型
で、bと同様のネジ穴6を設けたものである。放
熱板5とセラミツク基板1,1′との間の接着に
は第1図と同様の接着剤が使用できる。このよう
にして放熱板5を介在させると搭載する電子部品
2,2′にパワートランジスタ等の発熱性素子が
あつても、その放熱を効果的に行うことができ
る。 Figures 2a to 2c are block diagrams showing other embodiments of the present invention, in which copper is placed between ceramic substrates 1 and 1'.
The first point is that a heat sink 5 made of aluminum or the like is interposed.
Different from the illustration. Figures 2a and b show the SIL type; a is a type in which the upper end of the heat sink 5 is bent to transfer heat to the top cover of the equipment; It is something that heats up. Further, c is a DIL type and has a screw hole 6 similar to b. The same adhesive as shown in FIG. 1 can be used to bond the heat sink 5 and the ceramic substrates 1, 1'. By interposing the heat radiating plate 5 in this manner, even if there is a heat generating element such as a power transistor in the mounted electronic components 2, 2', the heat can be effectively radiated.
以上述べたように本考案によれば、セラミツク
基板同士の接着という簡単な工程を追加するだけ
でハイブリツド集積回路の集積度を倍化でき、ま
た、外部端子を基板に取付けるという簡単な工程
で両基板間を電気的に接続することができる。
As described above, according to the present invention, it is possible to double the integration density of a hybrid integrated circuit by simply adding the simple process of bonding ceramic substrates together, and it is possible to double the integration density of a hybrid integrated circuit by simply adding the simple process of attaching external terminals to the substrate. It is possible to electrically connect the substrates.
第1図は本考案の一実施例を示す構成図、第2
図は本考案の他の実施例を示す構成図、第3図お
よび第4図は従来のハイブリツド集積回路の異な
る例を示す構成図である。
図中、1,1′はセラミツク基板、2,2′は電
子部品、3は外部端子である。
Fig. 1 is a configuration diagram showing one embodiment of the present invention;
This figure is a block diagram showing another embodiment of the present invention, and FIGS. 3 and 4 are block diagrams showing different examples of conventional hybrid integrated circuits. In the figure, 1 and 1' are ceramic substrates, 2 and 2' are electronic components, and 3 is an external terminal.
Claims (1)
ンを形成して必要な電子部品を半田付けし、且
つ該2枚のセラミツク基板の他面同士を接着し
て一体化し、さらに両基板の端部を挟むように
両基板の配線パターンに共通接続される外部端
子を設けてなることを特徴とするハイブリツド
集積回路。 (2) 前記2枚のセラミツク基板が金属板を介して
接着されることを特徴とする実用新案登録請求
の範囲第1項記載のハイブリツド集積回路。[Scope of Claim for Utility Model Registration] (1) A wiring pattern is formed on each side of two ceramic substrates and necessary electronic components are soldered thereto, and the other surfaces of the two ceramic substrates are bonded together. A hybrid integrated circuit characterized by being integrated and further provided with external terminals commonly connected to the wiring patterns of both substrates so as to sandwich the ends of both substrates. (2) The hybrid integrated circuit according to claim 1, wherein the two ceramic substrates are bonded together via a metal plate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8913484U JPS614463U (en) | 1984-06-15 | 1984-06-15 | hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8913484U JPS614463U (en) | 1984-06-15 | 1984-06-15 | hybrid integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS614463U JPS614463U (en) | 1986-01-11 |
JPH0231794Y2 true JPH0231794Y2 (en) | 1990-08-28 |
Family
ID=30642918
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8913484U Granted JPS614463U (en) | 1984-06-15 | 1984-06-15 | hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS614463U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS566664B2 (en) * | 1975-03-10 | 1981-02-13 | ||
JPS599552B2 (en) * | 1971-08-04 | 1984-03-03 | ビイク グルデン ロンベルク ヒエ−ミツシエ フアブリ−ク ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for producing 4,4-diarylpiperidine |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5584980U (en) * | 1978-12-07 | 1980-06-11 | ||
JPS6027074Y2 (en) * | 1979-06-29 | 1985-08-15 | 日本ケ−ブル株式会社 | Buffer structure of damping ring for lift carrier |
JPS599552U (en) * | 1982-07-09 | 1984-01-21 | 株式会社日立製作所 | Hybrid thick film integrated circuit |
-
1984
- 1984-06-15 JP JP8913484U patent/JPS614463U/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS599552B2 (en) * | 1971-08-04 | 1984-03-03 | ビイク グルデン ロンベルク ヒエ−ミツシエ フアブリ−ク ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for producing 4,4-diarylpiperidine |
JPS566664B2 (en) * | 1975-03-10 | 1981-02-13 |
Also Published As
Publication number | Publication date |
---|---|
JPS614463U (en) | 1986-01-11 |
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