JPS5897969A - Control signal generating circuit of video camera - Google Patents

Abstract

PURPOSE:To generate a control signal for iris control, gain control, etc., by processing the output of a digital video camera through a microcomputer. CONSTITUTION:The video output of an image pickup element 1 is digitized by an AD converter 10 and supplied to a delay circuit 12 and horizontal split registers 13A-13C through an adder 11. Those delay circuit 12 and registers 13A-13C are controlled by a decoder 16 which receives outputs of horizontal and vertical scanning counters 17 and 18, and their outputs are supplied to the adder 11 through gates 14A-14C. Consequently, the registers 13A-13C supply mean data of blocks obtained by dividing an image pickup picture to a microcomputer 19 through a latch 15. The microcomputer 19 processes those data. In this case, the microcomputer 19 performs light measuring processing such as averaged light measuring and center-weighted measuring to control an iris 2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control signal generation circuit applied to, for example, a digital video camera.

Auto iris adjustment of conventional video cameras has been performed using the configuration shown in FIG. In the figure, 1 is an image sensor made of, for example, a CCD, 2 is an iris device, and the output from the image sensor 1 is sent to an amplifier 3 and an AGC circuit 4.
is led to the output terminal 5 via. The iris device 2 includes a motor and the like, and is configured to automatically set the iris according to an iris control signal. At the same time, the output of the AGC circuit 4 is transmitted to the gate circuit 6.
The output of the peak detection circuit T controls the iris device 2 and the AGC circuit 4. As shown in FIG. 2, a gate pulse is supplied to the gate circuit 6 from a gate pulse generator 8 to cause a gate-off period of about i of a /field (/V) period.

The same thing as the iris control described above can also be applied to a digital video camera, by multiplying the data corresponding to the gate pulse shown in FIG. 2 by the camera output, and finding the peak value or average value of the output. This allows you to control the iris device. However, in order to do so, it is necessary to add data for seven screens, and the number of bits in the result of the addition increases, resulting in a disadvantage that the hardware becomes large-scale. Also, if processing can be done with a microcomputer, the circuit size can be reduced, but since the data processing speed of the microcomputer is slower than the video data transmission ray), the gate and peak detection (or average value detection) processing described above is required. is impossible.

This invention makes it possible to generate control signals for iris control and gain control by processing the output of a digital video camera using small-scale hardware such as a microcomputer.

An embodiment of the present invention will be described below.

In this example, as shown in Fig. 3, the two-dimensional picture to be photographed is divided into nine blocks 9A to 9H, the video data included in each block is added, and the video data for each block is added. Data is sent to the microcontroller for processing.

FIG. 9 shows the configuration of an embodiment of the present invention, in which the output of the camera element 1 is converted by an A/D converter 10 into video data of, for example, /sample g bits, and an adder 11
supplied to The output of this adder 11 is supplied to a delay circuit 12 with a delay amount of /sample and registers 13A, 13B, and 130 in a number equal to the number of horizontal divisions. The output of this delay circuit 12 is supplied to the adder 11, and the outputs of the registers 13A, 13B, 13C are fed to the gate) 14.
Adder 11 and latch 15 via A, 14B, 14C
supplied to This register 13A is the block 9A,
The register 13B is for generating the addition output of the data included in each of blocks 9D and 9G.
, 9E, and 9H, and register 13C is associated with blocks 9C, 9F, and 9I. Also,
Reference numeral 16 denotes a decoder, to which outputs from a horizontal counter 17 and a vertical counter 18 are supplied. and,
The decoder 16 generates a clear pulse for the delay circuit 12, a control pulse for the registers 13A, 13B, and 13C, a gate pulse for the gates 14A, 14B, and 140, and a latch pulse for the latch 15.

The summed output for each block, that is, the average value data obtained from the latch 15 is supplied to the microcomputer 19, and data processing is performed according to a predetermined program. Blocks 9A-9
Assuming that each average value data of H is a~Di, the microcomputer 19 calculates coefficients Kl~Di for these average value data.
An iris control signal is generated by multiplying by - and adding the result. In other words, (KxDa+ means Db+KsDc
＋・・−・・・・・・・・・10・Di) calculation processing is performed.

Here, if the coefficients Ks, Kz, and Ks are set to 0, the - data at the top of the screen is made irrelevant. Furthermore, if only 6 is set to 1 among the coefficients corresponding to the center block 9E, and all other coefficients are set to 0, central photometry will be performed.

What kind of processing is performed by the microcomputer 19 is determined by the program. A control signal generated from the microcomputer 19 is supplied to the iris device 2, and the iris value is adjusted according to the level of the control signal.

The formation of the average value data for each block described above will be described in detail. From A/D converter 0, the first
When video data appears sequentially in the line, second line, etc., the adder 11 performs accumulation. Then, the accumulated data of the first line of block 9A is set in register 13A,
Next, after the delay circuit 12 is cleared, the accumulated data of the first line of block 9B is set in the register 13B by the same operation, and then the accumulated data of the first line of block 9C is set to the register 13B. The thing is register 13C
is set to If the data of the second colline occurs,
The gate 14A is turned on, the data stored in the register 13A is supplied to the adder 11, and the data of the co-line is further accumulated with respect to the accumulated data of the first line in the block 9A. Other block 9B.

The operation in block 9C is similar, and by repeating this operation, at a predetermined timing, the accumulated data of all the blocks 9 appears at the output of the delay circuit 12, and this is taken into the latch 15. , is sent to the microcomputer 19. Furthermore, the accumulated data of each of blocks 9B and 9C is also generated at the output of the delay circuit 12 at a predetermined timing, and the latch 1
5 to the microcomputer 19. Above block 9
Once the operations regarding people, 9B, and 9C are completed, similar operations are performed on blocks 9D, 9B, . . . 9F, and then similar operations are performed on blocks 9G, 9H, and 9I.

Note that, unlike the above embodiment, the maximum value data may be detected for each block and sent to the microcomputer.

As mentioned above, in this invention, the screen is divided into multiple blocks, the average value or maximum value for each block is formed, and this is calculated by a microcomputer, etc., so the data rate is reduced and the hardware is reduced. It becomes simple and can be processed using a microcomputer.

Note that the present invention may be applied to gain control that extracts only data in the center of the screen, such as when adjusting white balance.

[Brief explanation of drawings]

Fig. 7 is a block diagram used to explain the control signal generation of a conventional video camera, and Fig. 7 is a waveform diagram of its gate pulse.
FIG. 3 is a route map showing screen division according to an embodiment of the present invention;
FIG. 1 is a block diagram of one embodiment of the present invention. 1... Image sensor, 2......
iris device. 9A to 9I...Block, 11...
...Adder. 13A, 13B, 13C...Register,
19...Microcomputer. Agent Masatomo Sugiura Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] The two-dimensional image to be photographed is divided into a plurality of blocks, data processing is performed for each divided block, and the processed data for each block is supplied to an arithmetic circuit. A control signal generation circuit for a video camera that performs iris control or gain control of the camera output according to the output of the signal.