JPS6157759U - - Google Patents
Info
- Publication number
- JPS6157759U JPS6157759U JP1984140869U JP14086984U JPS6157759U JP S6157759 U JPS6157759 U JP S6157759U JP 1984140869 U JP1984140869 U JP 1984140869U JP 14086984 U JP14086984 U JP 14086984U JP S6157759 U JPS6157759 U JP S6157759U
- Authority
- JP
- Japan
- Prior art keywords
- iris
- frame memory
- circuit
- weighting
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Diaphragms For Cameras (AREA)
Description
第３図は１フレーム画面上でのアイリス検出に
寄与する度合を示す模式図、第２図は従来のゲー
ト生成方式を用いたオートアイリス回路の原理を
示すブロツク図、第１図は本考案のオートアイリ
ス回路のブロツク図、第４図は１フレーム画面を
ｍ：ｎにブロツク化した重みづけフレームメモリ
の例を示す模式図、第５図は変換テーブルメモリ
を用いた本考案第１の実施例のブロツク図、第６
図は乗算器を用いた本考案の第２の実施例のブロ
ツク図、第７図は変換テーブルメモリの説明図で
ある。
９：映像信号入力端子、１０：アイリス用映像
信号重みづけ回路、１１：アイリス制御部、１２
，１２ａ：重みづけフレームメモリ、１４：ブロ
ツクカウンタ、１５：変換テーブルメモリ、２３
：乗算器。
Fig. 3 is a schematic diagram showing the degree of contribution to iris detection on a single frame screen, Fig. 2 is a block diagram showing the principle of an auto-iris circuit using the conventional gate generation method, and Fig. 1 is a diagram showing the auto-iris circuit of the present invention. A block diagram of the circuit. Fig. 4 is a schematic diagram showing an example of a weighted frame memory in which one frame screen is divided into m:n blocks. Fig. 5 is a block diagram of the first embodiment of the present invention using a conversion table memory. Figure, 6th
The figure is a block diagram of a second embodiment of the present invention using a multiplier, and FIG. 7 is an explanatory diagram of a conversion table memory. 9: video signal input terminal, 10: iris video signal weighting circuit, 11: iris control section, 12
, 12a: weighting frame memory, 14: block counter, 15: conversion table memory, 23
: Multiplier.
Claims (1)
数のブロツクに分割し、各ブロツクに対応する映
像信号の重みづけ用データを記憶するフレームメ
モリと、上記テレビジヨンカメラの走査と同期し
て該フレームメモリに記憶された対応する重みづ
け用データを読出すメモリ制御回路と、上記フレ
ームメモリから得られるデータをもとに上記対応
する映像信号に重みづけを行なうアイリス用映像
信号重みづけ回路と、該アイリス用映像信号重み
づけ回路の出力に基づき、レンズのアイリスを制
御するアイリス制御回路を有することを特徴とす
るテレビジヨンカメラのオートアイリス回路。 a frame memory that two-dimensionally divides the imaging screen of the television camera into a plurality of blocks and stores data for weighting video signals corresponding to each block; and a frame memory that is synchronized with the scanning of the television camera. a memory control circuit for reading out the corresponding weighting data stored in the frame memory; a video signal weighting circuit for the iris that weights the corresponding video signal based on the data obtained from the frame memory; An auto iris circuit for a television camera, comprising an iris control circuit that controls the iris of a lens based on the output of a video signal weighting circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984140869U JPS6157759U (en) | 1984-09-19 | 1984-09-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984140869U JPS6157759U (en) | 1984-09-19 | 1984-09-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6157759U true JPS6157759U (en) | 1986-04-18 |
Family
ID=30699212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984140869U Pending JPS6157759U (en) | 1984-09-19 | 1984-09-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6157759U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20240080047A (en) | 2022-11-29 | 2024-06-05 | 고려대학교 산학협력단 | Wideband and high-efficiency power amplifier |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5897969A (en) * | 1981-12-05 | 1983-06-10 | Sony Corp | Control signal generating circuit of video camera |
-
1984
- 1984-09-19 JP JP1984140869U patent/JPS6157759U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5897969A (en) * | 1981-12-05 | 1983-06-10 | Sony Corp | Control signal generating circuit of video camera |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20240080047A (en) | 2022-11-29 | 2024-06-05 | 고려대학교 산학협력단 | Wideband and high-efficiency power amplifier |
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