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JPS588953U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS588953U
JPS588953U JP1981101431U JP10143181U JPS588953U JP S588953 U JPS588953 U JP S588953U JP 1981101431 U JP1981101431 U JP 1981101431U JP 10143181 U JP10143181 U JP 10143181U JP S588953 U JPS588953 U JP S588953U
Authority
JP
Japan
Prior art keywords
recess
semiconductor equipment
external connection
ceramic substrate
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981101431U
Other languages
Japanese (ja)
Inventor
岡野　一雄
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1981101431U priority Critical patent/JPS588953U/en
Publication of JPS588953U publication Critical patent/JPS588953U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置の断面図、第２図、第３図は
本考案による半導体装置の実施例の断面図、第４図は本
考案の半導体装置を半導体装置実装用基板に実装した様
子を示す断面図である。 １・・・・・・半導体素子、２・・・・・・パッケージ
、３・・・・・・金属細線、４・・・・・・パッケージ
内部電極、５・・・・・・メタライズ配線、６・・・・
・・スルーホール、７・・・・・・外部接続端子、８・
・・・・・リード、９・・・・・・樹脂枠体、１０・・
・・・・半田、１１・・・・・・半導体装置実装用基板
、１２・・・・・・メタライズ配線、１３・・・・・・
保護用樹脂。FIG. 1 is a cross-sectional view of a conventional semiconductor device, FIGS. 2 and 3 are cross-sectional views of an embodiment of a semiconductor device according to the present invention, and FIG. 4 is a cross-sectional view of a semiconductor device according to the present invention mounted on a semiconductor device mounting board. FIG. 3 is a sectional view showing the situation. 1...Semiconductor element, 2...Package, 3...Metal thin wire, 4...Package internal electrode, 5...Metallized wiring, 6...
...Through hole, 7...External connection terminal, 8.
...Lead, 9...Resin frame, 10...
... Solder, 11 ... Semiconductor device mounting board, 12 ... Metallized wiring, 13 ...
Protective resin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 中央部に凹部を有し該凹部の周囲に複数個の外部接続端
子を有するセラミック基板の前記凹部に半導体素子が載
置され、樹脂枠体で固定された複数の金属箔リードによ
り前記半導体素子の電極と前記セラミック基板上の外部
接続端子とが接続されていることを特徴とする半導体装
置。A semiconductor element is placed in the recess of a ceramic substrate having a recess in the center and a plurality of external connection terminals around the recess, and the semiconductor element is connected to the recess by a plurality of metal foil leads fixed with a resin frame. A semiconductor device characterized in that an electrode and an external connection terminal on the ceramic substrate are connected.
JP1981101431U 1981-07-08 1981-07-08 semiconductor equipment Pending JPS588953U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981101431U JPS588953U (en) 1981-07-08 1981-07-08 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981101431U JPS588953U (en) 1981-07-08 1981-07-08 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS588953U true JPS588953U (en) 1983-01-20

Family

ID=29896096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981101431U Pending JPS588953U (en) 1981-07-08 1981-07-08 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS588953U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS535596A (en) * 1976-07-05 1978-01-19 Sharp Corp Led display unit
JPS5355965A (en) * 1976-10-29 1978-05-20 Nec Corp Manufacture of semiconductor device
JPS5552687U (en) * 1978-09-30 1980-04-08

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS535596A (en) * 1976-07-05 1978-01-19 Sharp Corp Led display unit
JPS5355965A (en) * 1976-10-29 1978-05-20 Nec Corp Manufacture of semiconductor device
JPS5552687U (en) * 1978-09-30 1980-04-08

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