JPS58204541A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58204541A JPS58204541A JP8749782A JP8749782A JPS58204541A JP S58204541 A JPS58204541 A JP S58204541A JP 8749782 A JP8749782 A JP 8749782A JP 8749782 A JP8749782 A JP 8749782A JP S58204541 A JPS58204541 A JP S58204541A
- Authority
- JP
- Japan
- Prior art keywords
- oxygen content
- semiconductor
- specific resistance
- semiconductor device
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Investigating Or Analyzing Materials By The Use Of Fluid Adsorption Or Reactions (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は半導体素子の製造工程にある比抵抗変化全防止
する方法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for completely preventing changes in resistivity during the manufacturing process of semiconductor devices.
（−）技術の背景
近年、半導体素子はより巣墳度の高いものが要求され、
それに伴い半導体基板はますます欠陥の少ない高品質の
ものが要求さｎてハる。しかし、シリコン基板等半導体
基板には半導体結晶成長工程において結晶子に誘起され
た欠陥と素子形成工程子Ｏ熱処理工程において栢晶内部
に含でれている酸素や炭素等の不純物が原因ζなって発
生する欠陥（所謂、微小欠陥や積層欠陥）等がある。こ
れら各種欠陥は半導体装置の特性に悪影響を及ぼし歩留
りを低下させる原因となる。(-) Technology background In recent years, semiconductor devices have been required to have a higher degree of porosity.
As a result, high quality semiconductor substrates with fewer defects are increasingly required. However, semiconductor substrates such as silicon substrates are caused by defects induced in crystallites during the semiconductor crystal growth process and impurities such as oxygen and carbon contained within the crystallites during the element formation process and heat treatment process. There are defects that occur (so-called micro defects and stacking defects). These various defects adversely affect the characteristics of the semiconductor device and cause a decrease in yield.
（３）従来技術と問題点
これらの欠陥を防止する為に従来半導体素子形成工程前
に半導体基板裏面に傷を形成したり、或いはイオン注入
を行って欠陥の吸収源を形成しておくことにより、加熱
処理工程において発生する微小欠陥等を上記吸収源にゲ
ヅタさせる方法（Ｉｒｔｒｉｎｓｉｃ Ｇｅｔｔｅｒ
ｉｎｇ法）が行なわれて来た。−万、最近酸素不純物を
ある程度多く含んだ半導体基板を熱処理し、半導体基板
内の表面近傍にある余剰な酸素不純物を半導体基板外へ
拡散させ、半導体基板の内部のみに酸素析出物（ＳＩＸ
Ｏｙ）あるいはそれに起因する欠陥を作り、この欠陥に
素子形成工程中に発生する微小欠陥や積層欠陥の原因と
なる原子をゲッタさせ、半導体基板表面に無欠陥層（Ｄ
ｅｎｕｄｅｄ Ｚｏｎｅ ）を形成する所謂工Ｇ（Ｉ
ｎｔｒｉｎｓｉｃ Ｇｅｔｔｅｒｉｎｇ）法が盛んに
研究されている。(3) Prior art and problems In order to prevent these defects, conventional techniques have been used to form scratches on the back surface of the semiconductor substrate before the semiconductor element formation process, or to perform ion implantation to form defect absorption sources. Irtrinsic Getter
ing method) has been carried out. - Recently, a semiconductor substrate containing a certain amount of oxygen impurities has been heat-treated, and the excess oxygen impurities near the surface of the semiconductor substrate are diffused outside the semiconductor substrate, resulting in oxygen precipitates (SIX) only inside the semiconductor substrate.
A defect-free layer (D
The so-called engineering G (I
ntrinsic gettingtering) method is being actively researched.
上記工Ｇ法における熱処理温度９時間については様々な
組合せが報告されているが低温（６５０〜８００℃）に
おける数〜数十時間の熱処理工程は欠陥の核形成に有効
でありほとんどの工Ｇ法に含まれている。Various combinations of the heat treatment temperature for 9 hours in the above-mentioned Engineering G method have been reported, but the heat treatment process at a low temperature (650 to 800°C) for several to several tens of hours is effective for nucleation of defects, and most of the included in.
ところが、上記低温（６５０〜８００℃ ）における熱
処理においてドナーが生じシリコン基板の比抵抗が著し
く変化するという報告が、Ａｋｉｈｉｒ。However, Akihir reported that during the heat treatment at the low temperature (650 to 800°C), donors are generated and the resistivity of the silicon substrate changes significantly.
Ｋａｎａｍｏｒｉ ｅｔ ａｌ、、 Ｊ、 Ａｐｐ
ｌ、 Ｐｈｙ、、 ５０゜８０９５−＋３１０１．１９
ツ９やＶ、Ｃａｚｃａｒｒａ ｅｔａｌ、、 Ｊ、Ａｐ
ｐｌ、 ｆ’ｈｙ、 、 ５１．４２０６−４２１１゜
１９８０などに述べられている。しかし、上記ドナー（
Ｋａｎａｍｏｒｉらはこれを「Ｎｅｙ ＤｏｎｏｒＪ
と呼んでいる）の発生機種や原因についてはまだ明確
ではない。Kanamori et al., J. App.
l, Phy,, 50°8095-+3101.19
Tsu9ya V, Cazcarra etal, J, Ap
pl, f'hy, 51.4206-4211°1980. However, the above donor (
Kanamori et al.
The model and cause of the outbreak are still unclear.
（４）発明の目的
□
本発明の目的は、上記問題点を解決し、低温（６５０〜
８００℃）熱処理を有するＩＧ法において比抵抗変化を
防止し得る半導体素子の製造方法を提供しようとするも
のである。(4) Purpose of the invention □ The purpose of the present invention is to solve the above problems and to
The present invention aims to provide a method for manufacturing a semiconductor device that can prevent changes in resistivity in the IG method that includes heat treatment (800°C).
酸素含有量がイントリンシックゲッタリング（工Ｇ）効
果を生ずるに十分で、かつ３５ｐｐｍａ（Ｌ６ＸＩＯ１
ａ原子／ ｃｍ” ）以下の半導体結晶基板を用い、６
５０〜ＳＯＯ℃の低温熱処理を有するイントリンシック
ゲッタリング（工Ｇ）工程を素子形成工程中に有するこ
とを特徴とする半導体素子の製造方法を提供するもので
ある。The oxygen content is sufficient to produce an intrinsic gettering effect and 35 ppma (L6XIO1
Using a semiconductor crystal substrate of less than a atom/cm”,
The present invention provides a method for manufacturing a semiconductor device, characterized in that an intrinsic gettering (G) step having a low-temperature heat treatment at 50 to SOO° C. is included in the device formation step.
発明者らは前述の８５０〜８００℃の熱処理において生
じる比抵抗変化と酸素含有量に相関関係があり、酸素含
有量が３３ｐｐｍａ以下であれば比抵抗がほとんどない
ことを見い出したものである。The inventors have discovered that there is a correlation between the change in resistivity that occurs during the heat treatment at 850 to 800° C. and the oxygen content, and that when the oxygen content is 33 ppma or less, there is almost no resistivity.
（６）発明の実施例
以下に本発明による半導体素子の製造方法の一実施例に
ついて説明する。(6) Embodiment of the Invention An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described below.
用いた半導体基板はシリコンウェーハでいずれも市販さ
れている無転位の直径３インチのＣＺウェハーであり面
方位は（１，０，０）、ホウ素をドープした比抵抗７〜
２３Ω・国のものである。これら生ウェハー中の酸素含
有量はフーリエ変換型赤外分光器により測足し換算係数
は文献Ａ ８ Ｔ ＊１（Ｆ’１２１−７９）に従った
。鷹た比抵抗値は４点法により求め、熱処理は窒素雰囲
気中で行った。The semiconductor substrates used were silicon wafers, commercially available dislocation-free CZ wafers with a diameter of 3 inches, plane orientation (1,0,0), boron-doped resistivity 7~
It is 23Ω/country. The oxygen content in these raw wafers was measured using a Fourier transform infrared spectrometer, and the conversion coefficient was in accordance with the literature A 8 T *1 (F'121-79). The specific resistance value was determined by a four-point method, and the heat treatment was performed in a nitrogen atmosphere.
上記方法により求めた酸素含有量と比抵抗変化率の関係
を図に示す。図で縦軸は比抵抗変化率、横軸は酸素含有
量である。熱処理は′７００℃、２４時間のものである
。図より明らかなように、酸素含有量と比抵抗変化率に
は相関があり、酸素含有量が３３ｐｐｍａ以下であれば
比抵抗変化率は５優以内とほとんど変化しないことが分
かる。またＩＧ法における低温熱処理時間は多くの場合
２４時間以ドであるので実際の比抵抗変化率はより少な
く、酸素含有量３３ｐｐｍａ以下であれは該比抵抗変化
は問題にならない程度である。The relationship between the oxygen content and the specific resistance change rate determined by the above method is shown in the figure. In the figure, the vertical axis is the specific resistance change rate, and the horizontal axis is the oxygen content. The heat treatment was at '700°C for 24 hours. As is clear from the figure, there is a correlation between the oxygen content and the rate of change in specific resistance, and it can be seen that when the oxygen content is 33 ppma or less, the rate of change in specific resistance is within 5 or less and hardly changes. Furthermore, since the low-temperature heat treatment time in the IG method is often 24 hours or longer, the actual rate of change in resistivity is smaller, and if the oxygen content is 33 ppma or less, the change in resistivity is not a problem.
工」効果を起こさせるのに必要な酸素含有量はその工程
における熱処理温度や時間やそれらの組合せによりかな
り異なるが少なくとも２５〜３゜ｐｐｍａ（Ｌ２ＸＬ５
ＸＩＯ”６１Ｍ’以上含む必要がある。The oxygen content required to cause the heat treatment effect varies considerably depending on the heat treatment temperature, time, and combination thereof in the process, but it is at least 25 to 3°ppma (L2XL5
It is necessary to include XIO"61M' or more.
半導体結晶の酸素含有量ｆ＜ 工Ｇ効果を生じるのに十
分であり、かつ３３ｐｐｍａ以下の範囲に制御すること
は可能であり半導体結晶の製造に問題はない。The oxygen content f of the semiconductor crystal is sufficient to produce the engineering effect and can be controlled within the range of 33 ppma or less, so there is no problem in manufacturing the semiconductor crystal.
（〕）発明の詳細
な説明したごとく本発明を用いれば半導体素子の製造に
当り、比抵抗変化が生じることなく、従って半導体の特
性及び製造歩留が向上する。(2) Detailed Description of the Invention As described above, if the present invention is used in the manufacture of semiconductor devices, no change in resistivity will occur, thereby improving the characteristics of the semiconductor and the manufacturing yield.
図は、本発明の半導体素子の製造方法の実施例による酸
素含有量に対する比抵抗変化率の変化を示す。
〔ＳThe figure shows the change in specific resistance change rate with respect to oxygen content according to an embodiment of the method for manufacturing a semiconductor device of the present invention. [S
Claims (1)
導体結晶よりなる半導体基板を用い、６５０〜ａＯＯ℃
の低温熱処理を有するイントリンシックゲソタリング工
程を素子形成工程中に含むこと’ｋＷ徴とする半導体装
置の製造方法。Using a semiconductor substrate made of a semiconductor crystal with an oxygen content of 25 D p m q to 33 pma, the temperature was 650 to aOO°C.
A method for manufacturing a semiconductor device, which includes an intrinsic gesotaring step having a low-temperature heat treatment in a device forming step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8749782A JPS58204541A (en) | 1982-05-24 | 1982-05-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8749782A JPS58204541A (en) | 1982-05-24 | 1982-05-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58204541A true JPS58204541A (en) | 1983-11-29 |
Family
ID=13916601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8749782A Pending JPS58204541A (en) | 1982-05-24 | 1982-05-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58204541A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4851358A (en) * | 1988-02-11 | 1989-07-25 | Dns Electronic Materials, Inc. | Semiconductor wafer fabrication with improved control of internal gettering sites using rapid thermal annealing |
| US4868133A (en) * | 1988-02-11 | 1989-09-19 | Dns Electronic Materials, Inc. | Semiconductor wafer fabrication with improved control of internal gettering sites using RTA |
| US4994399A (en) * | 1989-05-16 | 1991-02-19 | Fujitsu Limited | Method of gettering heavy-metal impurities from silicon substrates by laser-assisted intrinsic gettering |
-
1982
- 1982-05-24 JP JP8749782A patent/JPS58204541A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4851358A (en) * | 1988-02-11 | 1989-07-25 | Dns Electronic Materials, Inc. | Semiconductor wafer fabrication with improved control of internal gettering sites using rapid thermal annealing |
| US4868133A (en) * | 1988-02-11 | 1989-09-19 | Dns Electronic Materials, Inc. | Semiconductor wafer fabrication with improved control of internal gettering sites using RTA |
| US4994399A (en) * | 1989-05-16 | 1991-02-19 | Fujitsu Limited | Method of gettering heavy-metal impurities from silicon substrates by laser-assisted intrinsic gettering |
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