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JPS594128A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS594128A
JPS594128A JP11316082A JP11316082A JPS594128A JP S594128 A JPS594128 A JP S594128A JP 11316082 A JP11316082 A JP 11316082A JP 11316082 A JP11316082 A JP 11316082A JP S594128 A JPS594128 A JP S594128A
Authority
JP
Japan
Prior art keywords
substrate
heat treatment
nitrogen
gas
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11316082A
Other languages
Japanese (ja)
Inventor
Akira Osawa
大沢 昭
Koichiro Honda
耕一郎 本田
Ritsuo Takizawa
滝沢 律夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11316082A priority Critical patent/JPS594128A/en
Publication of JPS594128A publication Critical patent/JPS594128A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain the semiconductor device whereon no change in carrier density is brought into the interior of a substrate and also the fluctuation of specific resistance can be prevented by a method wherein a heat treatment is performed on the semiconductor substrate in the inert gas atmosphere such as hydrogen gas or nitrogen gas containing hydrogen gas and the like. CONSTITUTION:After a heat treatment, as the first process, has been performed at 700 deg.C for 24hr in a nitrogen atmosphere on the silicon substrate formed by performing a CZ method, another heat treatnent as the second process is performed at 1,050 deg.C for three hours in the same nitrogen atmohphere, and then as the third process, a heat treatment is performed at 400 deg.C for ten minutes in an atmsophere containing the nitrogen gas of 5% of hydrogen gas and 95% of nitrogen gas in volume percentage. The first process above-mentioned is performed for the purpose of forming a deffective nuclear on the silicon substrate, and the second process is performed in orde to form a diffused zone by outdiffusing oxygen located on the surface of the substrate and, at the same time, to grow a defective nuclear. Through these procedures, the diffused zone is formed on the working region of the substrate after the second process has been completed, and the donor incidentally generated when the above diffused zone is formed disappears in the third process, thereby enabling to effectively prevent the fluctuations of specific resistance in the working region.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は、半導体基板の半導体素子形成領域にデニュー
デッドゾーンを形成し、且つ、内部に欠陥核を形成する
工程を含む半導体装置の製造方法の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to manufacturing a semiconductor device including a step of forming a denuded zone in a semiconductor element forming region of a semiconductor substrate and forming defect nuclei therein. Concerning improvements in methods.

(2)技術の背景 半導体素子にあって、良好な特性を確保するためには、
その基板に転位、積層欠陥等の結晶欠陥が存在しないこ
とが望ましい。半導体素子において、集積度の向上は非
常に重要な要請であり、このような高集積度半導体素子
にあっては、半導体素子の動作領域の寸法が極度に小さ
く、相対的に結晶欠陥の大きさが無視しえない状態にあ
り、上記の結晶欠陥の影響が着像し難いものとなってい
るからである。
(2) Technical background In order to ensure good characteristics of semiconductor devices,
It is desirable that crystal defects such as dislocations and stacking faults do not exist in the substrate. Improving the degree of integration is a very important requirement for semiconductor devices, and in such highly integrated semiconductor devices, the dimensions of the operating area of the semiconductor device are extremely small, and the size of crystal defects is relatively small. This is because the crystal defects cannot be ignored and the influence of the crystal defects described above makes it difficult to form an image.

ところで、シリコン(Sl)単結晶よりなる基板は、一
般にチョクラルスキー法(以下、CZ法という。)を使
用して製造されるが、この(EZ法により製造されたシ
リコン(Si)基板には、すでに、単結晶引き上げ時に
ルツボより不可避的に混入している酸素原子(0)等の
不純物が含まれており、これらの不純物が欠陥核となっ
てその後の半導体装置素子形成工程、特に、高温工程に
おいて結晶欠陥に成長する。この結晶欠陥を、上記の酸
素原子(0)等の状態で除去することは、現在の技術水
準では困難であるが、続く熱処理工程を利用して上記の
酸素原子(0)を除去することは可能であり、これによ
って、動作領域を無欠陥層(デニューデッドゾーン)と
するための様々な努力がなされてきた。
Incidentally, a silicon (Si) single crystal substrate is generally manufactured using the Czochralski method (hereinafter referred to as the CZ method), but this silicon (Si) substrate manufactured by the EZ method has , it already contains impurities such as oxygen atoms (0) that are unavoidably mixed in from the crucible during single crystal pulling, and these impurities become defect nuclei and cause problems in the subsequent semiconductor device element formation process, especially at high temperatures. During the process, crystal defects grow into crystal defects.It is difficult at the current state of technology to remove these crystal defects in the state of oxygen atoms (0), etc., but using the subsequent heat treatment process, the above oxygen atoms can be removed. It is possible to remove (0), and various efforts have been made to make the operating region a defect-free layer (denuded zone).

(3)従来技術と問題点 従来技術においては、半導体素子形成工程に先立ち、半
導体基板表面に傷を形成する、あるいは、イオン注入を
行う等の方法により欠陥の吸収源を形成し、続(熱処理
工程において発生する基板表面の結晶欠陥等を上記吸収
源に捕捉させる方法が使用されてきた。しかし、この方
法は付加的工程を伴なうばかりでなく、その捕捉効果も
必ずしも完全とは言い難いため、最近、酸素原子(0)
を不純物としてかなりの高濃度(1018/ ClTl
 3)に含んだシリコン(S t )基板に高温熱処理
を行うことにより、基板表面近傍の酸素原子(0)等の
不純物をアウトディフュージョンさせて除去し、かつ、
基板内部に酸素析出物(Sixty) 、あるいは、そ
れに起因する結晶欠陥を形成することにより、半導体素
子形成工程、特に、熱処理工程中に発生する微小欠陥や
積層欠陥を捕捉し、消滅させることにより、動作領域を
デニューデッドゾーンとする方法が実用化された。この
方法は、基板の深層に発生した結晶欠陥等の微小欠陥が
基板表面の有害不純物や欠陥を吸着し、消滅させるとい
う現象、いわゆる、イントリンシックゲッタリング現象
(以下、IG現象という。)を利用したもので、その有
用性が認められている。
(3) Prior art and problems In the prior art, prior to the semiconductor element formation process, defect absorption sources are formed by forming scratches on the semiconductor substrate surface or by ion implantation, followed by heat treatment. A method has been used in which crystal defects, etc. on the substrate surface generated during the process are captured by the above-mentioned absorption source.However, this method not only involves additional steps, but also its capture effect is not necessarily perfect. Therefore, recently, oxygen atom (0)
as an impurity at a fairly high concentration (1018/ClTl
By performing high temperature heat treatment on the silicon (S t ) substrate contained in 3), impurities such as oxygen atoms (0) near the substrate surface are removed by outdiffusion, and
By forming oxygen precipitates (Sixty) or crystal defects caused by them inside the substrate, we can trap and eliminate micro defects and stacking faults that occur during the semiconductor element formation process, especially during the heat treatment process. A method in which the operating area is a denuded dead zone has been put into practical use. This method utilizes the so-called intrinsic gettering phenomenon (hereinafter referred to as the IG phenomenon), in which microscopic defects such as crystal defects that occur deep in the substrate adsorb harmful impurities and defects on the substrate surface and eliminate them. Its usefulness has been recognized.

ところで、上記デニューデッドゾーンを形成する方法に
おいては、その熱処理の温度範囲や熱処理時間について
、様々な組み合わせが報告されており、枚挙にいとまが
ないが、そのうち550 (’C)〜900 (’C)
における数〜数十時間の低温熱処理工程が上記の欠陥核
形成に最も有効であることが認められており、この工程
が上記のいずれの方法においても含まれている。
By the way, in the method of forming the denuded dead zone, various combinations of heat treatment temperature range and heat treatment time have been reported, and there are too many combinations to list, but among them, 550 ('C) to 900 ( 'C)
It has been recognized that the low temperature heat treatment step for several to several tens of hours is the most effective for the formation of defect nuclei, and this step is included in all of the above methods.

ところが、上記の低温熱処理工程によって、基板の内部
にn型キャリアとして動作する新しいドナーが発生し、
それによってキャリア濃度が変化し、結果として基板の
比抵抗に変化をもたらすという欠点のあることが明らか
になった。
However, the above-mentioned low-temperature heat treatment process generates new donors that act as n-type carriers inside the substrate.
It has become clear that this has the disadvantage that the carrier concentration changes, resulting in a change in the resistivity of the substrate.

(4)発明の目的 本発明の目的は、上記の欠点を解消することにあり、半
導体基板の半導体素子形成領域にデニューデッドゾーン
を形成し、且つ、内部に欠陥核を形成する目的をもって
なす550 [’e)〜9oo〔℃〕における低温熱処
理工程を含む半導体装置の製造方法において、基板内部
にキャリア濃度の変化をもたらさない、すなわち、比抵
抗の変化を防止しうる半導体装置の製造方法を提供する
ことにある。
(4) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to form a denuded zone in a semiconductor element formation region of a semiconductor substrate, and to form defect nuclei therein. A semiconductor device manufacturing method including a low-temperature heat treatment step at 550 ['e) to 900 [°C], which does not cause a change in carrier concentration inside the substrate, that is, prevents a change in resistivity, is provided. It is about providing.

(5)発明の構成 本発明の構成は、半導体基板に、欠陥核を形成せしめる
低温熱処理を施した後、該半導体基板を水素(N2)ガ
スもしくはN2ガスを含む窒素(N2)ガス等の不活性
ガス雰囲気中で熱処理を行うことにある。
(5) Structure of the Invention The structure of the present invention is that after a semiconductor substrate is subjected to low-temperature heat treatment to form defect nuclei, the semiconductor substrate is treated with hydrogen (N2) gas or nitrogen (N2) gas containing N2 gas. The purpose is to perform heat treatment in an active gas atmosphere.

Cl法により製造されたシリコン’(S + )単fa
 高中に過飽和に含まれる酸素原子(0)は、55o〔
℃〕〜900 (’C)における低温熱処理工程におい
て析出し、格子欠陥を有する析出物(Sixty)を形
成することは周知である。
Silicon '(S+) single fa manufactured by Cl method
The oxygen atom (0) contained in supersaturated oxygen is 55o[
It is well known that precipitates (Sixty) having lattice defects are formed by precipitating in a low temperature heat treatment process at temperatures of 900° C. to 900° C.

本発明の発明者らは、このよう(こして形成された析出
物(Sixty)とシリコン(Si)単結晶母体との界
面には析出(Sixty)中の格子欠陥にょる不対結合
(1)angl ing Bond )が存在し、コノ
不対結合に関与する不対電子がドナーとして動作し、動
作領域のキャリア濃度を変化させる原因となっているの
で、上記の不対結合に水素原子(H)等を反応させるこ
とにより、安定な共有結合を生成させて不対結合を消滅
させればよいとの着想を得て、上記の反応を水素(N2
)ガスと窒素(N2)ガス等の不活性ガスをもって稀釈
した雰囲気中における熱処理工程をもって実現すること
となして、上記の着想を具体化して本発明を完成した。
The inventors of the present invention discovered that the interface between the precipitate (Sixty) thus formed and the silicon (Si) single crystal matrix has unpaired bonds (1) due to lattice defects in the precipitate (Sixty). angling Bond), and the unpaired electron involved in the cono unpaired bond acts as a donor, causing a change in the carrier concentration in the operating region. I got the idea that by reacting the like, stable covalent bonds could be generated and unpaired bonds could be eliminated.
) gas and an inert gas such as nitrogen (N2) gas, the present invention was completed by embodying the above idea.

また、特に上記の不対結合を消滅させるために実行され
る熱処理工程の温度範囲は、200 (”C)〜900
 [℃)とすると有効であることが、繰り返し実験を行
うことにより認められた。
In addition, the temperature range of the heat treatment step performed specifically to eliminate the above-mentioned unpaired bonds is 200 ("C) to 900C.
[°C] was found to be effective through repeated experiments.

(6)発明の実施例 本発明の一実施例に係る半導体装置の製造方法について
説明し、本発明の構成と特有の効果とを明らかにする。
(6) Embodiment of the Invention A method for manufacturing a semiconductor device according to an embodiment of the present invention will be explained, and the structure and unique effects of the present invention will be clarified.

Cl法により形成されたシリコン(Si)基板の動作領
域にデニューデッドゾーンを形成するために、半導体装
置素子形成工程において、上記の基板に対して2工程よ
りなる熱処理工程と、続いて、動作領域に発生したドナ
ーを消滅させるために1工程よりなる熱処理工程とを行
う。すなわち、第1工程として、窒X (N2)雰囲気
中において、700〔℃〕で24時間熱処理を行ったの
ち、第2工程として同じく室床(N2)雰囲気中におい
て、1,050[’C)で3時間熱処理を行い、次に第
3工程として、体積百分率で5 〔%〕の水素(N2)
ガスと95〔%〕の窒素(N2)ガスとを含む雰囲気中
において、400〔℃〕で10分間熱処理を行う。ここ
で、第1工程はシリコン(8i)基板に欠陥核を形成す
る為のもので、第2工程は基板表面の酸素をアウトディ
フュージョンしてデニューデッドゾーンを形成すると共
に欠陥核を成長させる為に行っている。
In order to form a denuded zone in the active region of a silicon (Si) substrate formed by the Cl method, in the semiconductor device element forming process, the above-mentioned substrate is subjected to a two-step heat treatment process, and then an operation process. A heat treatment step consisting of one step is performed to eliminate the donors generated in the region. That is, as a first step, heat treatment was performed at 700 [°C] in a nitrogen atmosphere (N2) for 24 hours, and then as a second step, heat treatment was performed at 1,050 [°C] in a room floor (N2) atmosphere. Heat treatment was performed for 3 hours at
Heat treatment is performed at 400 [° C.] for 10 minutes in an atmosphere containing gas and 95 [%] nitrogen (N2) gas. Here, the first step is to form defect nuclei on the silicon (8i) substrate, and the second step is to out-diffuse oxygen on the substrate surface to form a denuded zone and grow defect nuclei. I'm going to

上記の工程によれば、第2工程完了後に基板の動作領域
には、デニューデッドゾーンが形成され、その際付随的
に発生したドナーは、第3工程によって消滅し、動作領
域の比抵抗の変化が有効に防止される。
According to the above process, a denuded dead zone is formed in the active region of the substrate after the completion of the second step, and the donors incidentally generated at that time are annihilated in the third step, and the specific resistance of the active region is reduced. Changes are effectively prevented.

上記第1及び第2工程完了後に発生するドナー量と、上
記第1、第2及び第3工程完了後に発生するドナー量と
の比較を第1図に示す。図において、縦軸は、シリコン
(Si)基板の比抵抗の変化から換算された発生したド
ナー量(XIO” cm−3)であり、横軸は、シリコ
ン(Sl)基板に含有されていた酸素濃度(、ppln
 atoln )である。また、破線は、上記第1及び
第2工程完了後に発生するドナー量を示し、実線は、上
記第1、第2及び第3工程完了後に発生するドナー量を
示す。
FIG. 1 shows a comparison between the amount of donors generated after completing the first and second steps and the amount of donors generated after completing the first, second and third steps. In the figure, the vertical axis is the amount of generated donors (XIO" cm-3) converted from the change in resistivity of the silicon (Si) substrate, and the horizontal axis is the amount of oxygen contained in the silicon (Sl) substrate. Concentration (, ppln
atoln). Furthermore, the broken line indicates the amount of donors generated after completing the first and second steps, and the solid line indicates the amount of donors generated after completing the first, second, and third steps.

この図からも明らかなとおり、基板に対して第3工程を
含む熱処理工程を行うと、発生するドナー量は非常にわ
ずかとなり、第3工程を含まない熱処理を行った場合に
比し、特に高い酸素濃度において極めて顕著なドナー消
滅効果、すなわち、ドナー発生防止効果のあることが確
認された。
As is clear from this figure, when the substrate is subjected to a heat treatment process that includes the third process, the amount of donors generated is extremely small, and is particularly high compared to when heat treatment is performed that does not include the third process. It was confirmed that there is a very significant donor extinction effect, that is, an effect of preventing donor generation, depending on the oxygen concentration.

(7)発明の詳細 な説明せるとおり、本発明によれば、半導体基板の半導
体素子形成領域にデニューデッドゾーンを形成し、且つ
、内部に欠陥核を形成する目的をもってなす550[’
C)〜900[’C]における低温熱処理工程を含む半
導体装置の製造方法において、基板内部にキャリア濃度
の変化をもたらさない、すなわち、比抵抗の変化を防止
しつる半導体装置の製造方法を提供することができる。
(7) As described in detail, according to the present invention, the 550 ['
C) To provide a method for manufacturing a semiconductor device that does not cause a change in carrier concentration inside the substrate, that is, prevents a change in resistivity, in a method for manufacturing a semiconductor device including a low temperature heat treatment step at ~900['C]. be able to.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、700〔℃〕をもってなす第1工程と、1、
050 [:’Clをもってなす第2工程と、400[
’C)をもってなす第3工程とよりなる、本発明の一実
施例に係る半導体装置の製造方法に付随して発生したド
ナー量(実線)と、700(”Clをもってなす第1工
程と、1.050 (’C)をもってなす第2工程とよ
りなる従来技術における半導体装置の製造方法に付随し
て発生したドナー量(破線)とを、シリコン(Si)単
結晶に含まれる酸素濃度を独立変数として比較したグラ
フである。 代理人弁理士松岡宏四部
Figure 1 shows the first step performed at 700 [℃], 1.
050[:'The second step using Cl, and 400[:'
The amount of donors (solid line) generated accompanying the method of manufacturing a semiconductor device according to an embodiment of the present invention, which consists of the third step performed with 700 ("C), and the first step performed with 700 ("Cl), .050 ('C) and the amount of donors (dashed line) generated in the conventional semiconductor device manufacturing method consisting of the second step, and the oxygen concentration contained in the silicon (Si) single crystal as an independent variable. This is a graph comparing the following.Representative Patent Attorney Hiroshi Matsuoka

Claims (1)

【特許請求の範囲】[Claims] 半導体基板に、欠陥核を形成せしめる低温熱処理を施し
た後、該半導体基板を、水素ガスもしくは水素ガスを含
む不活性ガス雰囲気中で熱処理を行う工程を有すること
を特徴とする、半導体装置の製造方法。
Manufacture of a semiconductor device, comprising a step of subjecting a semiconductor substrate to low-temperature heat treatment to form defect nuclei, and then heat-treating the semiconductor substrate in an atmosphere of hydrogen gas or an inert gas containing hydrogen gas. Method.
JP11316082A 1982-06-30 1982-06-30 Manufacture of semiconductor device Pending JPS594128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11316082A JPS594128A (en) 1982-06-30 1982-06-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11316082A JPS594128A (en) 1982-06-30 1982-06-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS594128A true JPS594128A (en) 1984-01-10

Family

ID=14605067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11316082A Pending JPS594128A (en) 1982-06-30 1982-06-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS594128A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247935A (en) * 1984-05-23 1985-12-07 Toshiba Ceramics Co Ltd Manufacture of semiconductor wafer
JPS61183916A (en) * 1985-02-08 1986-08-16 Toshiba Corp Manufacture of semiconductor substrate
JPH01202828A (en) * 1988-02-08 1989-08-15 Toshiba Corp Manufacture of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247935A (en) * 1984-05-23 1985-12-07 Toshiba Ceramics Co Ltd Manufacture of semiconductor wafer
JPH0518254B2 (en) * 1984-05-23 1993-03-11 Toshiba Ceramics Co
JPS61183916A (en) * 1985-02-08 1986-08-16 Toshiba Corp Manufacture of semiconductor substrate
JPH01202828A (en) * 1988-02-08 1989-08-15 Toshiba Corp Manufacture of semiconductor device

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