JPS58153406A - Oscillator for voltage control - Google Patents
Oscillator for voltage controlInfo
- Publication number
- JPS58153406A JPS58153406A JP3559482A JP3559482A JPS58153406A JP S58153406 A JPS58153406 A JP S58153406A JP 3559482 A JP3559482 A JP 3559482A JP 3559482 A JP3559482 A JP 3559482A JP S58153406 A JPS58153406 A JP S58153406A
- Authority
- JP
- Japan
- Prior art keywords
- variable capacitance
- bias supply
- series
- circuit board
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J3/00—Continuous tuning
- H03J3/02—Details
- H03J3/16—Tuning without displacement of reactive element, e.g. by varying permeability
- H03J3/18—Tuning without displacement of reactive element, e.g. by varying permeability by discharge tube or semiconductor device simulating variable reactance
- H03J3/185—Tuning without displacement of reactive element, e.g. by varying permeability by discharge tube or semiconductor device simulating variable reactance with varactors, i.e. voltage variable reactive diodes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
Landscapes
- Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、可変容量ダイオードを直並列に多段に構成し
て実装した電圧制御即発振器(VCO)に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage controlled instant oscillator (VCO) in which variable capacitance diodes are arranged in series and parallel in multiple stages.
VCOは、−例として、第1図のように記述することが
でき、発振器の共振コイル1に直列に接続される共振部
のキャパシタンスの一部に、可変容量ダイオード2を用
いて、そのバイアス印加電圧(チューニング電圧vT)
により、キャパシタンスが変化することを利用して、そ
れ全結合回路3で共振コイル1に結合させ、とnらの共
蛋器と発振トランジスタ回路4とで決まる発振周波数を
変化させるようにしたものである。なお、トランジスタ
回路4の電源は、電源回路5から供給さ扛出力は、結合
回路6を経て取り出される。For example, a VCO can be described as shown in Fig. 1, in which a variable capacitance diode 2 is used to apply a bias to a part of the capacitance of the resonant part connected in series to the resonant coil 1 of the oscillator. Voltage (tuning voltage vT)
By using the fact that the capacitance changes, it is coupled to the resonant coil 1 by the fully coupled circuit 3, and the oscillation frequency determined by the oscillator and the oscillation transistor circuit 4 is changed. be. Note that the power to the transistor circuit 4 is supplied from a power supply circuit 5, and the output thereof is taken out via a coupling circuit 6.
通常、可変容量ダイオード回路2は、5g2図のように
示さn、したがってvCOに使用さnる可変容量ダイオ
ード7は1個あるいは多くて2個である。この場合には
、他の部品と同様にプリント基板に実装して差しつかえ
なかった。なお、チューニング電圧vTは、高周波チョ
ークコイル8で供給さnる。Usually, the variable capacitance diode circuit 2 is shown as shown in Fig. 5g2, so the number of variable capacitance diodes 7 used for vCO is one or at most two. In this case, it could be mounted on a printed circuit board like other parts. Note that the tuning voltage vT is supplied by a high frequency choke coil 8.
ところが、高性能・広螢域なりCOの実現のために、第
3図のように、可変容量ダイオードを直並列に多段に構
成する方法をとる場合においては、事情が異なってくる
。However, the situation becomes different when a method of configuring variable capacitance diodes in multiple stages in series and parallel as shown in FIG. 3 is used in order to realize high performance and wide range CO.
まず、この可変容量ダイオードを直並列に多段構成する
方法について述べると、第3図に示す接続法が最も部品
点数も少なく、効率的な方法であると考えら扛る。すな
わち、1個あるいは、複数個並列接続さ扛た可変容量ダ
イオード9,10゜11および12の同電極同志を背中
合わせの形で多段に接続し、各カソード接続部13,1
4には直流電圧が印加さ扛るような高周波チョーク等の
バイアス供給回路15 、16’i接続し、各アノード
接続部については、最下端にあるアノード接続部1゛7
は接地し、残りのアノード接続部18は、バイアス供給
回路19を介して直流的に接地するこの時、第4図の実
装平面図a、実装側面図すのように従来の延長では、可
変容量ダイオード9〜12f!:すべてプリント基板2
0に設けた電極パターンに実装することになる。この場
合、バイアス供給回路15,16.19は、高周波的に
充分に高インピーダンスだとしても、プリント基板20
がエポキシガラスの場合、各カソード接続部13゜14
の電極パターンとアース21との間、あるいは、各アノ
ード接続部のパターン18とアース21との間に、1〜
4PF8度の浮遊容量が存在するため可変容量値の絶対
値が大きくなり、実効的な容量可変幅が狭くなるという
欠点があった。この現象は、可変容量ダイオードを直列
に多段接続する程、可変ダイオード全体の容量が小さく
なるので、浮遊容量の影響が増大し顕著となる。′1.
た並列に多段接続する程、電極パターンが広くなるので
、浮遊容量が大きくなり、この場合も現象が顕著となる
。なお、第4図の実施例は、この第3図の回路接続図に
対応したものである。First, a method of configuring variable capacitance diodes in series and parallel in multiple stages will be described. The connection method shown in FIG. 3 is considered to be the most efficient method with the least number of parts. That is, one or more parallel-connected variable capacitance diodes 9, 10° 11, and 12 with the same electrodes are connected back-to-back in multiple stages, and each cathode connection portion 13, 1 is connected in multiple stages.
A bias supply circuit 15, 16'i such as a high frequency choke to which a DC voltage is applied is connected to 4, and each anode connection part is connected to an anode connection part 1'7 at the lowest end.
is grounded, and the remaining anode connection part 18 is DC grounded via the bias supply circuit 19. At this time, as shown in the mounting plan view a and the mounting side view of FIG. Diode 9~12f! : All printed circuit board 2
It will be mounted on the electrode pattern provided at 0. In this case, even if the bias supply circuits 15, 16, and 19 have sufficiently high impedance in terms of high frequency, the printed circuit board 2
If is made of epoxy glass, each cathode connection 13°14
between the electrode pattern and the ground 21, or between the pattern 18 of each anode connection part and the ground 21.
Since there is a stray capacitance of 4PF8 degrees, the absolute value of the variable capacitance value becomes large, resulting in a drawback that the effective capacitance variable width becomes narrow. This phenomenon becomes more noticeable as the variable capacitance diodes are connected in series in multiple stages, as the overall capacitance of the variable diodes becomes smaller, so the effect of stray capacitance increases and becomes more noticeable. '1.
As the electrode patterns are connected in parallel in multiple stages, the electrode pattern becomes wider, so the stray capacitance becomes larger, and the phenomenon becomes more pronounced in this case as well. The embodiment shown in FIG. 4 corresponds to the circuit connection diagram shown in FIG. 3.
また、浮遊容量がもたらす別の欠点として、以下のよう
なことがあげられる。VCOとしての動作時には、可変
容量ダイオードの各段には高周波電圧がかかることにな
る。可変容量ダイオードの並列接続の合計が1段あたり
Cv、浮遊容量C8は各段等しいとすると、N段時総容
量CMはバイアス供給回路が高周波的に高インピーダン
スであるとして、以下のようになる。Further, other drawbacks caused by stray capacitance include the following. When operating as a VCO, a high frequency voltage is applied to each stage of the variable capacitance diode. Assuming that the sum of the parallel connections of variable capacitance diodes is Cv per stage and the stray capacitance C8 is equal for each stage, the total capacitance CM at N stages is as follows, assuming that the bias supply circuit has high impedance at high frequencies.
C,=CV+C8
従って、各段毎に、等価容量が1/Nずつとならないの
で、各段にかかる高周波電圧にアンバランス全土ずるこ
とになる。浮遊容量C8−0ならば各段毎の等価容量は
1/Nずつとなる。高周波電圧アンバランスであると、
高周波電圧の大きくかかる段が生じ、そこでは、可変ダ
イオードの非線形歪の影響が大きくなり、受信機として
は、同調ずn1混変調妨害、 C/N (搬送波と雑音
の比) ′の劣化等が発生する。そのため浮遊容量を
減らし可変容量ダイオードにかかる高周波電圧のアンバ
ランスを減じる必要がある。C,=CV+C8 Therefore, since the equivalent capacitance of each stage is not equal to 1/N, the high frequency voltage applied to each stage will be unbalanced. If the stray capacitance is C8-0, the equivalent capacitance of each stage is 1/N. If there is a high frequency voltage imbalance,
There is a stage where a large amount of high-frequency voltage is applied, where the influence of nonlinear distortion of the variable diode becomes large, and the receiver suffers from untuned n1 cross-modulation interference, deterioration of C/N (carrier-to-noise ratio), etc. Occur. Therefore, it is necessary to reduce the stray capacitance and reduce the unbalance of the high frequency voltage applied to the variable capacitance diode.
本発明は、その浮遊容量が小さくなるような構造にして
、周波数可変幅の拡大等、vcoの特注向上を図ったも
のである。The present invention aims to improve customization of the VCO, such as by increasing the variable frequency range, by creating a structure that reduces stray capacitance.
第5図、第6図および第8図に、本発明の実施例を示す
。Embodiments of the present invention are shown in FIGS. 5, 6, and 8.
第3図のように直並列に同電極同志で多段接続さt′し
た可変容量ダイオード9〜12の実装法として、第5図
の例ではカソード電極接続部13.14が、本体プリン
ト基板20に設けた電極パターンを用いるのではなく、
ハンダ付けその他により直接的に、高周波チョーク等の
バイアス供給回路15.16とともに空間的に接続さt
ているのが特徴である。この実装法によp空間的に接続
さnた可変容量ダイオードのカソード電極接続部13゜
14と、本体プリント基板2oのアースパターン21と
は距離が離nその間の浮遊容量を大幅に減らすことがで
きる。なお17.18はアノード電・j接続部であり、
この場合前者はアース篭慎21と接続または兼用となっ
ている。As shown in FIG. 3, as a mounting method for variable capacitance diodes 9 to 12 connected in series and parallel with the same electrodes in multiple stages t', in the example shown in FIG. Rather than using a prepared electrode pattern,
Spatially connected directly with the bias supply circuit 15, 16, such as a high frequency choke, by soldering or otherwise.
It is characterized by With this mounting method, the distance between the spatially connected cathode electrode connection parts 13 and 14 of the variable capacitance diode and the ground pattern 21 of the main body printed circuit board 2o is large, and the stray capacitance between them can be significantly reduced. can. Note that 17.18 is the anode/j connection part,
In this case, the former is connected to or also serves as the earth shield 21.
第6図の実施例も、第5図とほんど同様であり同じ部位
には同じ番号を付しその説明も省略するが可変容量ダイ
オード9,10,11.12と、バイアス供給回路15
.16等の、接続のためのカソード電極接続部j3.1
4金パターン状に補助基板22に設は浮遊容量は小さく
、実装が容易で確実にした例である。ただし、この補助
基板22には、浮遊容量を減らすためにもアースパター
ンは設けず、本体プリント基板2oから浮かして部品を
立体的に実装するための保持として使用するだけである
。The embodiment of FIG. 6 is almost the same as that of FIG. 5, and the same parts are given the same numbers and their explanations are omitted.
.. Cathode electrode connection part j3.1 for connection, such as 16
This is an example in which the auxiliary substrate 22 is provided with a 4-metal gold pattern, which has a small stray capacitance and is easy and reliable to mount. However, in order to reduce stray capacitance, this auxiliary board 22 is not provided with a ground pattern, and is only used as a holder for three-dimensionally mounting components by floating it from the main printed board 2o.
さらに具体的な実施例で説明を行なうと、可変容量ダイ
オードを偶数個直列に接続する場合、−例として第7図
のような可変容量ダイオードが並列に6個、直列に4個
ずつ接続さnている場合について考える。図において並
列に接続さnている可変容量ダイオード25〜30の6
個を一つの可変容量ダイオード群31として考え、同様
に他の6個並列の可変容量ダイオード群を、そnぞれ可
変容量ダイオード群32.33.34とする。13及び
14はカソード電極接続部17.18及び23はアノー
ド電極接続部15,16.19及び24はバイアス供給
回路を示す。To explain with a more specific example, when an even number of variable capacitance diodes are connected in series, - for example, six variable capacitance diodes are connected in parallel and four in series as shown in FIG. Consider the case where In the figure, 6 of the variable capacitance diodes 25 to 30 are connected in parallel.
In the same way, the other six variable capacitance diode groups connected in parallel are considered to be variable capacitance diode groups 32, 33, and 34, respectively. 13 and 14 are cathode electrode connection portions 17, 18 and 23 are anode electrode connection portions 15, 16, and 19 and 24 are bias supply circuits.
第7図の回路構成の本発明に係る実装法を第8図に示す
。aは平面図、bは側面図、Cは正面図であり、第7図
と番号は対応させである。本実施例ではカソード電極接
続部13.14を本体グリ7 −ト基板2oから浮かせ
てワイヤ、ハンダその他で直接的に接続する。この実装
法はアノード側電極接続部17.18.23が、本体プ
リント基板に接続さn1力ソード側電極接続部13.1
4が空間的に接続さ汎るというように可変容量ダイオー
ドの電極の方向かすべて同じ方向を向いているので組立
ミスを生じにくく、実装も容易である。捷た、プリント
基板上のアノード側電極接続部18゜23にはバイアス
供給回路19.24が接続さn直流的に接地さn(なお
アノード電極接続部17は直接アー・スとなり、アース
パターン21と同じである)、また空間的に接続さnる
カソード側電極接続部13.14にはバイアス供給回路
15゜16が接続され、直流チー−ニング電圧vTが供
給されるというようにバイアス供給回路の実装にも統一
がと扛る。この実装法は第8図のす、cの側面図のよう
に可変容量ダイオードをプリント基板に立てて実装する
ので、実装スペースが小さく済み小形化に適している。FIG. 8 shows a method of mounting the circuit configuration of FIG. 7 according to the present invention. A is a plan view, b is a side view, and C is a front view, and the numbers correspond to those in FIG. 7. In this embodiment, the cathode electrode connecting portions 13, 14 are suspended from the main grid substrate 2o and directly connected with wires, solder, or the like. In this mounting method, the anode side electrode connection part 17.18.23 is connected to the main body printed circuit board.
Since the electrodes of the variable capacitance diodes are all oriented in the same direction, such as 4 being spatially connected, assembly errors are less likely to occur and mounting is easy. A bias supply circuit 19.24 is connected to the anode-side electrode connection portion 18.23 on the printed circuit board that has been disconnected and is grounded in a direct current manner (the anode electrode connection portion 17 is directly grounded and connected to the ground pattern 21). ), and the bias supply circuits 15 and 16 are connected to the spatially connected cathode side electrode connection parts 13 and 14, and the bias supply circuit is supplied with the DC-cheating voltage vT. There is also a need for uniformity in the implementation. In this mounting method, the variable capacitance diode is mounted upright on the printed circuit board as shown in the side view of FIG. 8, so the mounting space is small and it is suitable for miniaturization.
本発明の電圧制御発振器は以下に示す効果を有する。The voltage controlled oscillator of the present invention has the following effects.
すなわち電極接続部と、アース間の距#を遠ざけること
ができ、浮遊容量を減らすことができる。That is, the distance between the electrode connection portion and the ground can be increased, and stray capacitance can be reduced.
その結果可変容量ダイオードの全体の容量の絶対値が大
きくなり容量可変幅が狭くなるという浮遊容量の影=w
i小さくすることができ。As a result, the absolute value of the overall capacitance of the variable capacitance diode increases and the variable capacitance width narrows, which is the effect of stray capacitance = w
i can be made smaller.
また、可変容量ダイオード全体の実装面積を小さくする
ことができ、小形化に適している。また実装面積が同じ
場合であれば、プリント基板上にある電4 パターンと
アースパターンとを離す距離に余裕を得ることができ、
浮遊容量を小さくすることができる。Furthermore, the mounting area of the entire variable capacitance diode can be reduced, making it suitable for miniaturization. Also, if the mounting area is the same, you can get some margin in the distance between the electrical pattern and the ground pattern on the printed circuit board.
Stray capacitance can be reduced.
以上述べたように、本発明によりは直並列に同電極同志
で多段接続さnた可変容量ダイオードの一部または全部
を、プリント基板より浮かして実装することにより、可
変容量ダイオードの電倹とアース間の浮遊容量を低減し
、浮遊容量が原因で発生する等価容量の増加、容量可変
幅の縮少、加わる高周波電圧のアンバランス等の現象の
影4を小さくすることができること、および小形化に適
すること等の利点があシ、その工業的価値はきわめて大
きい。As described above, according to the present invention, by mounting part or all of the variable capacitance diodes connected in series and parallel in multiple stages with the same electrodes floating above the printed circuit board, the power saving and grounding of the variable capacitance diodes can be reduced. By reducing the stray capacitance between It has many advantages such as suitability, and its industrial value is extremely large.
第1図は電圧制御発振器(VCO)の系統図、第2図は
vCOの可変容量ダイオード回路の結線図、第3図は、
直並列に多段接続された可変容量ダイオード回路の結線
図、第4図dは、第3図の回路の従来の実装状態を示す
平面図、第4図すはその側面図、第5図は本発明の一実
施例の実装状態を示す側面図、第6図は本発明の別の実
施列の実装状態を示す側面図、第7図は他の具体的実施
−例の図、第8図aは、第7図の回路の本発明の実装状
態を示す平面図、bはその側面図、Cは正面図である。
1・・・・・・・共振コイル、2・・・・・・可変容量
ダイオード回路、3・・・・・・結合回路、4・・・・
・・発振トランジスタ回路、6・・・・・電源回路、6
・・・・・・結合回路、7・・・・・ 可変容量ダイオ
ード、8・・・・・・バイアス用高周波チョークコイル
、9〜12・・・・・・可変容量ダイオード群、13,
14・・・・・ カンード酸極接続部(パターン、15
.16・・・・・バイアス供給回路、17・・・・・・
アノード電極パターン(アースパターンと同一)、18
・・・・・アノード電極接続部(パターン)、19・・
・・・バイアス供給回路、2oぜ・・・・・(本体)プ
リント基板、21・・・・・・アースパターン、22・
・・・・補助基板、23・・・・・アノード電極接続部
(パターン)、24・・・・・・バイアス供給回路、2
6〜30・・・・・ 可変容量ダイオード、31〜34
・・・・・可変容量ダイオード群。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
第2図 第3図
第4図
第5図
第6図
−Vτ
第7図Figure 1 is a system diagram of a voltage controlled oscillator (VCO), Figure 2 is a wiring diagram of a vCO variable capacitance diode circuit, and Figure 3 is a diagram of a voltage controlled oscillator (VCO).
A wiring diagram of a variable capacitance diode circuit connected in series and parallel in multiple stages, Fig. 4d is a plan view showing the conventional mounting state of the circuit in Fig. 3, Fig. 4 is a side view thereof, and Fig. 5 is a diagram of the main circuit. FIG. 6 is a side view showing the mounting state of one embodiment of the invention; FIG. 6 is a side view showing the mounting state of another embodiment of the invention; FIG. 7 is a diagram of another specific embodiment; FIG. 8a 7 is a plan view showing a state in which the present invention is implemented in the circuit of FIG. 7, b is a side view thereof, and C is a front view thereof. 1... Resonant coil, 2... Variable capacitance diode circuit, 3... Coupling circuit, 4...
...Oscillation transistor circuit, 6...Power supply circuit, 6
...... Coupling circuit, 7... Variable capacitance diode, 8... High frequency choke coil for bias, 9 to 12... Variable capacitance diode group, 13,
14... Cando acid electrode connection part (pattern, 15
.. 16...Bias supply circuit, 17...
Anode electrode pattern (same as ground pattern), 18
...Anode electrode connection part (pattern), 19...
...Bias supply circuit, 2oze...(main body) printed circuit board, 21...earth pattern, 22...
... Auxiliary board, 23 ... Anode electrode connection part (pattern), 24 ... Bias supply circuit, 2
6-30... Variable capacitance diode, 31-34
...Variable capacitance diode group. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 - Vτ Figure 7
Claims (2)
極同志を直列に多段に接、読し、各カソード接続部には
、直流電圧が印加されるバイアス供給回路を接続し、ア
ノード接続部については、一方の最端にあるものだけ接
地し、残りのアノード接続部は、バイアス供給回路を介
して直流的に接地するように構成するとともに前記アノ
ード接続部あるいは、カソード接続部の一部あるいは全
部を直接、プリント基板上に設けらnた電極を利用して
接続せずに可変容量ダイオードのバイアス供給回路とと
もに、空間的にプリント基板より浮かせて接続したこと
を特徴とする電圧制御発振器。(1) The same electrodes of a plurality of variable capacitance diodes connected in parallel are connected in series in multiple stages, and a bias supply circuit to which DC voltage is applied is connected to each cathode connection, and the anode connection is , only the one at the extreme end is grounded, and the remaining anode connections are configured to be DC grounded via a bias supply circuit. 1. A voltage controlled oscillator characterized in that the entire part is not directly connected using electrodes provided on the printed circuit board, but is connected together with a bias supply circuit of a variable capacitance diode spatially above the printed circuit board.
し、プリント基板上にアノード接続部を設はカソード接
続部はバイアス供給回路とともに空間的に、プリント基
板より浮かせて接続(たことを特徴とする特許請求の範
囲第1項記載の電圧制御発振器。(2) It has an even number of variable capacitance diodes connected in series, and the anode connection part is set on the printed circuit board, and the cathode connection part is connected spatially above the printed circuit board together with the bias supply circuit. A voltage controlled oscillator according to claim 1, characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3559482A JPS58153406A (en) | 1982-03-05 | 1982-03-05 | Oscillator for voltage control |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3559482A JPS58153406A (en) | 1982-03-05 | 1982-03-05 | Oscillator for voltage control |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58153406A true JPS58153406A (en) | 1983-09-12 |
JPH0221684B2 JPH0221684B2 (en) | 1990-05-15 |
Family
ID=12446119
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3559482A Granted JPS58153406A (en) | 1982-03-05 | 1982-03-05 | Oscillator for voltage control |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58153406A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS621412U (en) * | 1985-06-19 | 1987-01-07 |
-
1982
- 1982-03-05 JP JP3559482A patent/JPS58153406A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS621412U (en) * | 1985-06-19 | 1987-01-07 | ||
JPH0453044Y2 (en) * | 1985-06-19 | 1992-12-14 |
Also Published As
Publication number | Publication date |
---|---|
JPH0221684B2 (en) | 1990-05-15 |
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