JP2558294B2 - Amplifier circuit IC - Google Patents
Amplifier circuit ICInfo
- Publication number
- JP2558294B2 JP2558294B2 JP62244261A JP24426187A JP2558294B2 JP 2558294 B2 JP2558294 B2 JP 2558294B2 JP 62244261 A JP62244261 A JP 62244261A JP 24426187 A JP24426187 A JP 24426187A JP 2558294 B2 JP2558294 B2 JP 2558294B2
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- power supply
- package
- output pin
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 claims description 18
- 238000010586 diagram Methods 0.000 description 7
- 230000003321 amplification Effects 0.000 description 6
- 238000003199 nucleic acid amplification method Methods 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000004088 simulation Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Bipolar Integrated Circuits (AREA)
- Microwave Amplifiers (AREA)
- Amplifiers (AREA)
Description
【発明の詳細な説明】 （１）発明の目的 ［産業上の利用分野］ 本発明は、高周波帯で安定な動作を確保できるように
した増幅回路ICに関するものである。DETAILED DESCRIPTION OF THE INVENTION (1) Object of the Invention [Field of Industrial Application] The present invention relates to an amplifier circuit IC capable of ensuring stable operation in a high frequency band.
［従来の技術］ 従来、広帯域高利得な増幅回路ICを実現する場合、第
３図に示すように各増幅段毎に電源を分割し、個別に電
源を供給することにより、従来のようなICチップ外の電
源供給用ボンディングワイヤ，ラインの寄生インダクタ
ンスの影響で、信号がICチップ内の電源ラインパタンを
介してまわり込むことができなくなり、発振などの不安
定動作に対して改善を図ることができる。[Prior Art] Conventionally, in the case of realizing an amplifier circuit IC with a wide band and high gain, as shown in FIG. 3, the power supply is divided for each amplification stage, and the power is individually supplied to the conventional IC. Due to the effect of the parasitic inductance of the power supply bonding wires and lines outside the chip, it becomes impossible for signals to sneak through the power supply line pattern inside the IC chip, and it is possible to improve unstable operation such as oscillation. it can.
特に発振の生じ易い高利得、高周波増幅回路ICでは、
電源を分割して供給することにより大きく安定性を確保
することができる（特開昭60−178657号公報参照）。同
図中１は入力端子、２は出力端子、３−１〜３−ｎは第
１の電圧源群、４−１〜４−ｎは第２の電圧源群、L11
〜L1n、L21〜L2nは各寄生インダクタンス、A1〜Anは各
増幅回路の各増幅段、αはICチップ、Vcc1〜Vccn,VEE1
〜VEEnは各増幅回路A1〜Anの電源用パッド群をそれぞれ
示す。Especially in the high gain and high frequency amplifier circuit ICs where oscillation is likely to occur,
Large stability can be ensured by dividing the power supply (see JP-A-60-178657). In the figure, 1 is an input terminal, 2 is an output terminal, 3-1 to 3-n are first voltage source groups, 4-1 to 4-n are second voltage source groups, and L11.
~ L1n, L21 ~ L2n are each parasitic inductance, A1 ~ An are each amplification stage of each amplifier circuit, α is IC chip, Vcc1 ~ Vccn, VEE1
~ VEEn are the power supply pad groups of the amplifier circuits A1 to An, respectively.
次に具体的に第４図に示すバイポーラ増幅回路ICの特
性について述べる（特開昭62−78903号公報および「並
列帰還形高利得IGHz帯Siモノリシックリミッタ増幅回
路」、昭和62年信学会総合全国大会、NO.356参照）。Next, the characteristics of the bipolar amplifier circuit IC shown in FIG. 4 will be concretely described (Japanese Patent Laid-Open No. 62-78903 and "Parallel feedback type high gain IGHz band Si monolithic limiter amplifier circuit", Showa 62 general nationwide society. See the competition, NO.356).
第５図は、ICの利得周波数特性のシミュレーション結
果を示す。FIG. 5 shows a simulation result of the gain frequency characteristic of the IC.
但し、電源用パッドVcc1〜Vcc4には6V、VEE1〜VEE4に
はOVを印加する。利得39dB、3dB帯域が約2.2GHZの特性
が得られている。However, 6V is applied to the power supply pads Vcc1 to Vcc4 and OV is applied to VEE1 to VEE4. The gain of 39dB and the characteristic of 3dB band are about 2.2GHZ.
以上述べた特性はセラミック基板上に電源安定化のた
めのバイパスコンデンサを出来るだけ大きく与え（数千
PF程度）で評価している。The characteristics described above give the bypass capacitor for stabilizing the power supply on the ceramic substrate as large as possible (thousands of thousands).
It is evaluated by PF).
一方、この増幅回路ICを使用する場合、パッケージ実
装した方がICが表面に露出せず信頼性の点ですぐれてい
るが、その場合次に述べる特性上の問題が生ずる。On the other hand, when this amplifier circuit IC is used, package mounting is superior in reliability because the IC is not exposed on the surface, but in that case, the following characteristic problem occurs.
第６図は、第４図の増幅回路ICをパッケージβに実装
した状態を示す図で、L11〜L14,L21〜L24はボンディン
グワイヤのインダクタンス、L31〜L34はパッケージβ内
のラインのインダクタンス、C11〜C14は電源安定化のた
めのバイパスコンデンサ、５−１〜５−４はパッケージ
出力ピンである。ここでボンディングワイヤのインダク
タンスL11〜L14,L21〜L24＝0.5nH、パッケージ内ライン
のインダクタンスL31〜L34＝5nH、バイパスコンデンサC
11〜C14はパッケージβ内に実装できるチップコンデン
サの最大値として100PF程度を与えた。また入出力の取
り出し用のボンディングワイヤのインダクタンスLIN,Lo
ut＝1nHを与えた。FIG. 6 is a diagram showing a state where the amplifier circuit IC of FIG. 4 is mounted in the package β, L11 to L14, L21 to L24 are inductances of bonding wires, L31 to L34 are inductances of lines in the package β, and C11. C14 are bypass capacitors for stabilizing the power supply, and 5-1 to 5-4 are package output pins. Here, the bonding wire inductance L11 to L14, L21 to L24 = 0.5nH, the package line inductance L31 to L34 = 5nH, the bypass capacitor C
About 11 to C14, about 100PF was given as the maximum value of the chip capacitor that can be mounted in the package β. In addition, the inductance of the bonding wire for taking out the input / output, LIN, Lo
ut = 1nH was given.
第７図にこの増幅回路ICの利得周波数特性を示す。 FIG. 7 shows the gain frequency characteristic of this amplifier circuit IC.
同図より200MHz付近で共振点が見られる。 From the figure, a resonance point can be seen near 200 MHz.
これは主に実装の寄生インダクタンスL31〜L34及びバ
イパスコンデンサC11〜C14による共振のために生じてい
る。This is mainly due to resonance due to the mounting parasitic inductances L31 to L34 and the bypass capacitors C11 to C14.
以上述べたようにパッケージβ内にバイパスコンデン
サC11〜C14を搭載し、増幅回路ICを実装した場合、利得
周波数特性において共振点が見られ、動作が不安定とな
る欠点を有していた。As described above, when the bypass capacitors C11 to C14 are mounted in the package β and the amplifier circuit IC is mounted, there is a drawback that a resonance point is seen in the gain frequency characteristic and the operation becomes unstable.
［発明が解決しようとする問題点］ 本発明は、利得周波数特性上に現われる共振点の影響
を小さくし、動作の安定を図った増幅回路ICを提供せん
とするものである。[Problems to be Solved by the Invention] The present invention intends to provide an amplifier circuit IC in which the influence of the resonance point appearing on the gain frequency characteristic is reduced and the operation is stabilized.
（２）発明の構成 ［問題点を解決するための手段］ 本発明の第１の特徴は、パッケージ化された増幅回路
ICにおいて、供給用電源に接続されるパッケージ出力ピ
ンと、前記増幅回路ICと同じパッケージ内に搭載され、
かつ前記増幅回路ICの電源用パッドと一端が接続される
とともに、他端が接地されたバイパスコンデンサと、前
記電源用パッドと前記パッケージ出力ピンとを接続した
電源供給用ラインと、前記パッケージ内に搭載され、前
記バイパスコンデンサと前記電源用パッドとの間に接続
された抵抗とを備えた増幅回路ICの構成採用にある。(2) Configuration of the Invention [Means for Solving the Problems] The first feature of the present invention is to provide a packaged amplifier circuit.
In the IC, the package output pin connected to the power supply for supply, and mounted in the same package as the amplifier circuit IC,
Also, a bypass capacitor having one end connected to the power supply pad of the amplifier circuit IC and the other end grounded, a power supply line connecting the power supply pad and the package output pin, and mounted in the package And adopting a configuration of an amplifier circuit IC including a resistor connected between the bypass capacitor and the power supply pad.
本発明の第２の特徴は、パッケージ化された増幅回路
ICにおいて、供給用電源に接続されるパッケージ出力ピ
ンと、前記増幅回路ICと同じパッケージ内に搭載され、
かつ前記増幅回路ICの電源用パッドと一端が接続される
とともに、他端が抵抗を介して接地されたバイパスコン
デンサと、前記電源用パッドと前記パッケージ出力ピン
とを接続した電源供給用ラインとを備えた増幅回路ICの
構成採用にある。A second feature of the present invention is a packaged amplifier circuit.
In the IC, the package output pin connected to the power supply for supply, and mounted in the same package as the amplifier circuit IC,
And a bypass capacitor having one end connected to the power supply pad of the amplifier circuit IC and the other end grounded via a resistor; and a power supply line connecting the power supply pad and the package output pin. The adoption of the configuration of the amplifier circuit IC.
［実施例］ 以下、本発明に係る増幅回路ICを、実施例に基づいて
詳細に説明する。[Examples] Hereinafter, the amplifier circuit IC according to the present invention will be described in detail based on Examples.
（第１実施例） 第１図は第１実施例の結線回路を示す。(First Embodiment) FIG. 1 shows a wire connection circuit of the first embodiment.
図中１は入力端子、２は出力端子、３−１〜３−４は
電圧源端子群、５−１〜５−４はパッケージ出力ピン、
７−１〜７−４はリード線、A1〜Anは各増幅回路の各増
幅段、αはICチップ、Vcc1〜Vccn、VEE1〜VEEnは各増幅
回路A1〜Anの電源用パッド群、L11〜L14、L21〜L24はボ
ンディングワイヤの寄生インダクタンス、L31〜L34はパ
ッケージβ内電源供給用ライン６−１〜66−４の寄生イ
ンダクタンス、C11〜C14はバイパスコンデンサ、R11〜R
14は共振のＱを下げるため付加した抵抗を示す。In the figure, 1 is an input terminal, 2 is an output terminal, 3-1 to 3-4 are voltage source terminal groups, 5-1 to 5-4 are package output pins,
7-1 to 7-4 are lead wires, A1 to An are amplification stages of each amplification circuit, α is an IC chip, Vcc1 to Vccn, VEE1 to VEEn are power supply pad groups of each amplification circuit A1 to An, and L11 to L14 and L21 to L24 are parasitic inductances of bonding wires, L31 to L34 are parasitic inductances of the power supply lines 6-1 to 66-4 in the package β, C11 to C14 are bypass capacitors, and R11 to R14.
Reference numeral 14 denotes a resistance added to lower the Q of resonance.
抵抗R11〜R14は、増幅回路ICのパッケージβ内に搭載
され、バイパスコンデンサC11〜C14の前に直列に挿入介
接されている。このため抵抗R11〜R14での電圧降下がな
く、回路動作への悪影響がない。The resistors R11 to R14 are mounted in the package β of the amplifier circuit IC and are inserted and connected in series in front of the bypass capacitors C11 to C14. Therefore, there is no voltage drop across the resistors R11 to R14, and there is no adverse effect on circuit operation.
（第２実施例） 第２図は第２実施例の結線回路を示す。(Second Embodiment) FIG. 2 shows a wire connection circuit of the second embodiment.
同図の記号は第１図と同じであるので、重複説明を省
略した。Since the symbols in the figure are the same as those in FIG. 1, duplicate explanations are omitted.
本実施例の増幅回路ICは、抵抗R11〜R14をバイパスコ
ンデンサC11〜C14の後に直列に挿入介接させた点が、第
１実施例と異なる。The amplifier circuit IC of the present embodiment is different from the first embodiment in that the resistors R11 to R14 are inserted and connected in series after the bypass capacitors C11 to C14.
以上説明した第１及び第２実施例の増幅回路ICによれ
ば、小さな抵抗をバイパスコンデンサC11〜C14の前後に
直列に付加するだけで共振のＱが下がり、増幅回路ICの
安定な動作が得られるという効果を奏する。According to the amplifier circuit ICs of the first and second embodiments described above, the resonance Q is lowered and stable operation of the amplifier circuit IC is obtained only by adding a small resistor in series before and after the bypass capacitors C11 to C14. The effect of being able to be played.
（３）発明の効果 かくして本発明では、広帯域高利得の増幅回路ICの利
得周波数特性上に現れる共振点の影響を減少させるに当
たり、増幅回路ICのバイパスコンデンサの前後に抵抗を
付加する構成を採用している。したがって、電圧降下を
伴う動作電流にて集積回路の電源電圧が揺らぐことがな
く、当該増幅回路ICを安定に動作できるという優れた効
果を奏する。(3) Effects of the Invention Thus, in the present invention, in order to reduce the influence of the resonance point appearing on the gain frequency characteristics of the amplifier circuit IC with wide band and high gain, a configuration in which a resistor is added before and after the bypass capacitor of the amplifier circuit IC is adopted. are doing. Therefore, the power supply voltage of the integrated circuit does not fluctuate due to the operating current accompanied by the voltage drop, and the excellent effect that the amplifier circuit IC can be stably operated is achieved.
第１図は本発明の第１実施例の結線回路図、第２図は本
発明の第２実施例の結線回路図、第３図は従来の増幅回
路ICの実装状態の結線回路図、第４図はバイポーラ増幅
回路図、第５図は第３図示の回路の利得周波数特性のシ
ミュレーション曲線図、第６図乃至第７図はバイポーラ
増幅回路の実装状態の結線回路図とその利得周波数特性
のシミュレーション曲線図である。 A1〜An……増幅回路 C11〜C14……バイパスコンデンサ L11〜1n,L21〜2n,L31〜34……寄生インダクタンス R11〜R14……抵抗 Vcc1〜VccN,VEE1〜VEEn……電源用パッド α……ICチップ β……パッケージ １……入力端子 ２……出力端子 ３−１〜３−n,4−１〜４−ｎ……電圧源 ５−１〜５−４……パッケージ出力ピン ６−１〜６−４……電源供給用ライン ７−１〜７−４……リード線FIG. 1 is a wiring circuit diagram of a first embodiment of the present invention, FIG. 2 is a wiring circuit diagram of a second embodiment of the present invention, and FIG. 3 is a wiring circuit diagram of a conventional amplifier circuit IC in a mounted state. FIG. 4 is a bipolar amplifier circuit diagram, FIG. 5 is a simulation curve diagram of the gain frequency characteristic of the circuit shown in FIG. 3, and FIGS. 6 to 7 are wiring circuit diagrams of the mounted state of the bipolar amplifier circuit and its gain frequency characteristic. It is a simulation curve figure. A1 to An …… Amplification circuit C11 to C14 …… Bypass capacitor L11 to 1n, L21 to 2n, L31 to 34 …… Parasitic inductance R11 to R14 …… Resistance Vcc1 to VccN, VEE1 to VEEn …… Power supply pad α …… IC chip β …… Package 1 …… Input terminal 2 …… Output terminal 3-1 to 3-n, 4-1 to 4-n …… Voltage source 5-1 to 5-4 …… Package output pin 6-1 ~ 6-4 ... power supply line 7-1 to 7-4 ... lead wire
Claims (2)
記増幅回路ICの電源用パッドと一端が接続されるととも
に、他端が接地されたバイパスコンデンサと、 前記電源用パッドと前記パッケージ出力ピンとを接続し
た電源供給用ラインと、 前記パッケージ内に搭載され、前記バイパスコンデンサ
と前記電源用パッドとの間に接続された抵抗と、を備え
た、 ことを特徴とする増幅回路IC。1. In a packaged amplifier circuit IC, a package output pin connected to a power supply for supply and a package output pin mounted in the same package as the amplifier circuit IC and connected at one end to a power supply pad of the amplifier circuit IC A bypass capacitor whose other end is grounded, a power supply line connecting the power supply pad and the package output pin, and a space between the bypass capacitor and the power supply pad mounted in the package. An amplifier circuit IC, comprising: a resistor connected to.
記増幅回路ICの電源用パッドと一端が接続されるととも
に、他端が抵抗を介して接地されたバイパスコンデンサ
と、 前記電源用パッドと前記パッケージ出力ピンとを接続し
た電源供給用ラインと、を備えた、 ことを特徴とする増幅回路IC。2. In a packaged amplifier circuit IC, a package output pin connected to a power supply for supply and a package output pin mounted in the same package as the amplifier circuit IC and having one end connected to a power supply pad of the amplifier circuit IC An amplifier circuit IC, further comprising: a bypass capacitor whose other end is grounded via a resistor; and a power supply line connecting the power supply pad and the package output pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62244261A JP2558294B2 (en) | 1987-09-30 | 1987-09-30 | Amplifier circuit IC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62244261A JP2558294B2 (en) | 1987-09-30 | 1987-09-30 | Amplifier circuit IC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6489707A JPS6489707A (en) | 1989-04-04 |
| JP2558294B2 true JP2558294B2 (en) | 1996-11-27 |
Family
ID=17116120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62244261A Expired - Lifetime JP2558294B2 (en) | 1987-09-30 | 1987-09-30 | Amplifier circuit IC |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2558294B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7501914B2 (en) | 2004-04-28 | 2009-03-10 | Mitsubishi Electric Corporation | Bias circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6074467A (en) * | 1983-09-30 | 1985-04-26 | Toshiba Corp | Mos type integrated circuit |
-
1987
- 1987-09-30 JP JP62244261A patent/JP2558294B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6489707A (en) | 1989-04-04 |
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