JPS58103063A - matrix storage - Google Patents

Abstract

PURPOSE:To shorten the processing time, by accessing two-dimensional data in parallel in the vertical direction as well as the horizontal direction in the system where two-dimensional arranged data is calculated and processed. CONSTITUTION:Memory modules 300-333 which are arranged in a matrix and have memory parts 3 having the two-dimensional arrangement and data switches 4 and 5 respectively, horizontal and vertical data busses XB0-XB3 and YB0- YB3, and a controlling mechanism which selects memory modules 300-333 and addresses of memory parts 3 in accordance with the access direction and the address and operates data switches 4 and 5 to select which data busses of data busses XB0-XB3 and YB0-YB3 should be connected respectively memory parts 3 in accordance with the access direction are provided. Thus, the device is so constituted that a number of data which is equal to the number of memory modules 300-333 in the line or column direction are accessed in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a matrix storage device, and more particularly to a matrix storage device suitable for data storage in a processing device that handles two-dimensional array data processing such as image data processing.

In systems that process two-dimensional array data, such as image data processing devices, there are many processes in which data is read out from memory in a vertical or horizontal direction and then processed, and much of the processing time is spent in memory. The time is spent on operations to retrieve data in this order.

In order to access (read and retrieve) continuous data quickly, it is effective to access data at consecutive adjacent addresses simultaneously and in parallel.Even in the main memory of conventional computers, memory is arranged in parallel. A method of simultaneous and parallel access was adopted.

However, when two-dimensional array data is accessed continuously, for example, if the addresses are continuous in the horizontal direction, the addresses when accessed continuously in the vertical direction are discrete addresses that span several units in the horizontal direction. Therefore, in the conventional parallel access method, there is no parallelization effect in the operation of successively retrieving data in the vertical direction (or data in the horizontal direction), and there is a drawback that a large processing time is required.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and to provide a matrix storage device that can access two-dimensional array data in parallel in both the vertical and horizontal directions.

The present invention provides a memory module having a memory section arranged in a matrix and each family of which has a two-dimensional array and a data switch, horizontal and vertical data buses, and the memory according to the access direction and its address. A control mechanism and complete equipment that has the function of selecting the address of the module and the memory part therein, and operating the data switch to select which of the data buses each memory part should be connected to according to the access direction. There is something that shows the percentage.

Hereinafter, the present invention will be explained in more detail from Example V.

FIG. 1 is an explanatory diagram of two-dimensional array data and continuous access thereof, and an array D2 in the figure is assumed to store two-dimensional data in a memory having a matrix-like structure. That is, this memory has a total capacity of 16 words (8 bits), an address 'k 1 byte) is expressed in the thickness direction.

For example, when fetching data from this memory, first, in horizontal order, Xo 'jo r XI Yo...
・・X127 Change YOS line to XOy, l x,
One is to take out in the order of y, "", and the other is to take out in the vertical order: Xo Yo * Xo Y+ + ""...Xo
In some cases, the data may be taken out in the order of Y+tr, XI yo l, etc. by changing the column. In order to speed up this retrieval, in the present invention, for example, four consecutive pieces of data are accessed in parallel, and
As shown in (Horizontal reading), there is a device that allows high-speed reading in any direction.

In addition, in conventional devices, retrieval in only one direction, for example, as shown in box Y in Figure 1, is achieved by dividing the memory into four parts and storing two-dimensional data in them using the inner leap method. , was also widely used in the main memory of conventional computers.

However, since it can only be parallelized as shown in FLY in FIG. 1, for example, when trying to obtain continuous data in the horizontal direction, first, as shown in R1 in FIG. 2, the first column of array D2 is Access the second column four times, etc., and take out the first column of the data column 1 obtained in this way again and put it on the board as shown in column 2 in Figure 2. Due to the changing operations, it was not possible to achieve both speeds because they were performed sequentially.

An embodiment of the present invention that solves these problems is shown in the block diagram of FIG. The storage device 1 in this example includes a random access memory (RAMJ3), each of which is made up of the storage body.
．． Consisting of data switches 4 and 5fr, memory modules 300 to 333 (16 pieces), data bus switches 6 and 7, memory module control circuit 8, and data bus switch control circuit 9, processing for accessing this storage device 1 The device 2 has a control circuit 1O, address counters 11 and 12, and 13 data registers.

Data switches 4 and 5 and data bus switches 6 and 7 are for forming a data path between the AM 3 and the data register 13 according to the total access content, 8 memory module control circuits, and memory modules 300 to 33.
The data bus switch control @1 circuit 9 is for distributing selection commands for each of R, AM3 and opening/closing commands for data switches 4 and 5. A pair of address counters 11 and 12fl are used to specify the address of the storage device fill, and a data register 3 is a device that mediates all the data exchange between the storage device 1 and the processing device 2. A control circuit 10 is a device for specifying the address of the storage device fill. While issuing a movement command to 1,
Address counters 11.12 related to memory accesses
and for controlling the data register 13.

The data input/output ports of each R, AM 3 of the memory modules 300 to 333 are connected to an internal data bus XBO to connect memory modules in the same column via a data switch 4.
XB3 is connected to each of internal data buses YBO to YB3, which connect comrades in the same row via a data switch 5, and internal data buses XEO-XE3 and YBO-Y are connected to each other.
B3 and % are integrated into one parallel data bus DB and coupled to data register 13 via data bus switch 7 and data bus switch 6, respectively.

- The control signal from the control circuit mio and the address designation signal from the address register 11.12 are passed through the entire memory module control circuit 8 to the memory modules 300-
333 (in FIG. 3, the signal routes from the module control circuit 8 to the memory modules 300 to 333 are omitted from the second column to avoid clutter in the drawing).

FIG. 4 shows details of the functions of each block in FIG. 3.

RAM3 stores 8-bit IK word data, and when you specify an address to terminal A1 (5 bits J, A2 (5 bits), a read or borrow function to terminal WE, and give terminal C3KIH), , terminal DO (8
The data is read from the data log of the bit. Each of the memory modules 300 to 333 is provided with a memory module selection circuit 14 and a data switch side tilt circuit 15 for starting the AM 3 and fully controlling the opening/closing of the data switch 4.5. Decoders 16 and 17 are provided in the memory module control circuit 8, and decoders 16 and 17 are provided for the lower two bits of the address counters 11 and 12, respectively.
It is decoded and distributed to the module selection circuit 14. Outputs XO to X3 of the decoders 16 and 17. YO
-Y3 and memory modules 300 to 333 correspond to memory module blocks 300 to 333 in FIG.
(XO, YO) ~ (X3.Y31) For example, the module selection circuit 14 of the memory module 300 has the XO ratio output of the decoder 16 and the YO high The upper 5 bits of address counters 11 and 12 are commonly connected to RAM3 of all memory modules, and Ft, AM3
Specifies the address of the internal IK word. Control time t1?
5io, the control #1 given to the storage device 1 includes a signal W/RF'UNCTIO that specifies the read/write transfer direction.
N and 1 Y/XMO that specifies whether data specific to the storage device of the present invention is to be accessed vertically or horizontally])E
These control signals are sent to the module selection circuit 14 and data switch control circuit 15 of all memory modules, and the data bus switch control circuit 9.
, AJ43 is started with the above XO to X3, or YO
~Y3 to switch whether to perform the data switch 4
．． 5, and data bus switch 6°7.

FIG. 5 shows the address information (Xo~+*r;Yo~8,7) of the X address counter 11 and the Y address counter 12 (9) and the memory module number (XO~ X3. Shown as YO~Y3)
The address correspondence of RAM 3 is shown below.

That is, first, as shown in Figure 1, an array (two-dimensional data JD2t
If it is 128 x 128 bytes, it is divided into small matrices of 4 bytes x 4 bytes in order from the top left in accordance with the 4 x 4 array of this D2i memory module. In this way, 32 (
= 128/4)×32 small matrices can be arranged, so
If these are given the representations CI, Jl (I, J = 0 to 31), each element of the 4x4 small matrix (I, Jl) will be expressed as Allocate one to each element in the column.Here, each RAM is IK bytes (the exact VC is 1024 bytes, so 32X
One summation from each of the 32=1024 sub-matrices is fitted to exactly each RAM K. Each frame in Figure 5 has one [
(, AM3'ik is represented, and the allocation result in the interleap method as described above is the address (
It is shown in the form of 1.

Now, with the above configuration, "o" t- is set as the initial value of address counter 11° (10) 12, and control circuit 1
When YlXMODE of 0 is set to a 1 pr,
Among the memory modules 300 to 333, the RAM of the memory modules 300, 310, 320, and 330 in the first row
3 is activated, the data switch 4 and data spring switch 7 of the same memory module are turned on, and are coupled to the data register 13, and the data register 13 has the first row indicated by BY in FIG. data is obtained.

Next, when the value of the X address counter 11 is increased by 4, the first
Obtain all the data on the second line of figure FLX. When the value of the X address counter 11 becomes 124, next, add 1 to the value of the X address counter 12 to obtain the value of the X address counter 12.
When it returns to @Q 071, it moves to the row of the memory module 301 and obtains all the data in the direction indicated by R and Y in FIG. 1 in sequence.

Next, in the “oil” control circuit 9, set YlXMODE all parameters to 0″’
and set the initial values of address counters 11 and 12 to 0".
In this case, the memory module is 300°301.30
2,303 RAM 3 is activated (11), and at the same time, the data switch 5 and the data bus switch 6 are closed to be coupled to the data register 13, and the data register 13 has the first BY of FIG. The data on the row is obtained, and the value of the X address counter 12 is +
4, and when the value of the X address counter 12 reaches 124, the address counter 11 . In history, vertical data 'f1: obtained sequentially. It is assumed that the update control of the address counter is included in the control circuit 10, and a detailed explanation of the specific means will be omitted.

The above is an explanation of continuous reading from the address (xoyo J), but it goes without saying that arbitrary values can be set in the address counters 11 and 12 to allow random access.

However, it should be noted that, for example, in the operation mode in the Y direction in FIG. 1, the value of the lower two bits of the (However, it is natural that the data at the address in question is included.) This (12) is not limited to the device of the present invention, but occurs in parallel access in general, and is therefore the object of the present invention. It is not something that hinders.

Furthermore, although the above embodiments have been described using specific values such as the size of two-dimensional data and the number of memory modules, it is easy to convert these values into films.

As is clear from the above description, according to the present invention, it is possible to access two-dimensional data in parallel in both the vertical and horizontal directions.For example, when the number of parallels is 4, compared to the conventional Compared to parallelization, the average throughput of vertical and horizontal continuous access can be improved by 2.5 times.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of two-dimensional array data and its parallel reading, FIG. 2 is an explanatory diagram of a conventional reading method, FIG. 3 is an overall block diagram showing an embodiment of the present invention, and FIG. Figure 2 shows the detailed logical configuration of the embodiment, Figure 5 shows the RAM
FIG. (13J 1... Matrix storage device, 2... Processing device, 3...
...RAM, 4.5...Data switch, 6.7...
・Data bus switch, 8...Memory module control circuit, 9...Data bus switch, control circuit, 14.
...Memory module selection circuit% 15...Data switch control circuit, 16.17...Address decoder,
XBO~XB3. YBO~YB3...Data bus. Agent: Patent attorney Masami Akimoto (14j

Claims (1)

[Claims] 1. A plurality of memory modules arranged in a matrix, each including a memory section having an array structure, a column direction data switch, and a row direction data switch, and each column of the memory module arrangement. a column direction data bus coupled to the memory section of each memory module in each row of the memory module array via the column direction data switch; and a column direction data bus coupled to the memory section of the memory module in each row of the memory module array via the row direction data switch. a row-direction data bus, and a selection mechanism that selects either the column-direction data buses or each row-direction data bus and connects the selected data bus to a processing device. The memory units in the memory modules arranged in one column or row of the memory module array are activated in parallel according to a command from the processing device, and the column or row direction switch in the memory module is turned on, and the above-mentioned and a control mechanism for controlling the selection mechanism to connect a column or row data bus connecting all of the activated memory modules to the processing unit, thus increasing the number of memory modules in the column or row direction of the array. A matrix storage device characterized by being configured so that an equal number of data can be accessed in parallel.