JPH0415555B2 - - Google Patents

Description

[Detailed description of the invention]

[Summary] The entire chip is divided into a desired rectangular bit collection (n
×m bits) according to N blocks (N=n×m)
The same row decoder is provided for each m block, and each row decoder is given the row address A _R or the adjacent row address A _R +1. Similarly, the same column decoder is provided for each n block. , by giving column address A _C or adjacent column address A _C +1 to each column decoder, memory cells of N bits are accessed from each block, and the desired memory cells are rearranged by rearranging the accessed memory cells. This is a boundary-free semiconductor memory device in which a rectangular bit aggregate is accessed, and it does not impair large capacity or high integration, and the rectangular shape also has a flexible character. [Industrial Application Field] The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a so-called boundary-free semiconductor memory device that is capable of simultaneously accessing not only data in a memory cell specified by an address signal, but also data in a plurality of memory cells surrounding the memory cell in a two-dimensional direction. The semiconductor memory device according to the present invention is suitably used for multidimensional data processing such as image data processing. [Prior Art] For example, in image processing, an image memory is used to store image data, and this image memory stores image data corresponding to an image displayed on a graphic display, for example. There are many. The image data stored in such image memory can be subjected to (1) compression, (2) difference taking, (3) smoothing, and other data processing between data stored in adjacent addresses. is often the case. In order to perform such data processing, it is necessary to read and process data not only in the target memory cell but also in the peripheral memory cells. Therefore, in such an image memory, etc., it is required to be able to quickly access not only the target memory cell but also the peripheral memory cells. In addition, such requirements are not limited to access for each memory cell, but also for each word in matrix calculations, three-dimensional data processing, etc., and a function that can read stored data at adjacent addresses at high speed will improve these processes. This will improve efficiency. FIG. 17 is a circuit diagram showing a conventional semiconductor memory device, in which not only the target memory cell but also the surrounding memory cells can be accessed, but there is an address boundary (reference:
Figure 2 of Publication No. 59-180324). That is, word lines WL0, WL1, WL2,... and bit lines BL0,
Memory cells MC00, MC01, MC02,..., MC connected between BL1, BL2, BL3,...
10, MC11, ... and each bit line BL0, BL1,
BL2, BL3, ... and data buses DB0, DB1,
It is composed of transfer transistors Q ₀ , Q ₁ , Q ₂ , Q ₃ , ... connected between DB2 and DB3, and a column decoder CD0 etc. that commonly controls Q ₀ to Q ₃ of these transistors. be done. In the storage device shown in FIG. 17, one word line, for example WL1, is selected and the column decoder
Word line WL1 is selected by applying a column selection signal from CD0 to each transistor Q ₀ , Q ₁ , Q ₂ , Q ₃
For example, it is possible to access 4-bit memory cells MC01, MC11, MC21, and MC31 among the memory cells connected to the memory cells, and to read these data simultaneously onto each data bus DB0, DB1, DB2, and DB3. That is, in the memory device shown in FIG. 17, so-called parallel reading is possible in which 4 bits of data are read out simultaneously by one address specification. However, in FIG. 17, the memory cells to which parallel reading is performed are limited to those connected to predetermined bit line groups, and memory cells connected to different groups of bit lines cannot be read simultaneously. I couldn't do it. Therefore,
For example, the target memory cell is memory cell MC31.
When the memory cells are connected to the bit lines at both ends of one data line group, it is impossible to read out the memory cells on both sides of the intended memory cell at the same time. In other words, an address boundary existed. For this reason, the applicant has already proposed an address boundary-free semiconductor memory device that does not have an address boundary (see: Japanese Patent Application Laid-Open No. 1983-1996).
180324, Japanese Patent Application Laid-open No. 61-58058). Such a semiconductor memory device will be explained with reference to FIGS. 18 and 19. FIG. 18 is a block circuit diagram showing a conventional boundary-free semiconductor memory device (see Japanese Patent Laid-Open No. 180324/1983). That is, in FIG. 18, word lines WL0, WL1, WL2,...
Bit lines BL0, BL1, BL2, ... and memory cells MC00, MC01, MC02, connected between these word lines and bit lines, respectively.
...; MC10, MC11, MC12..., three data buses DB-1, DB0, DB+1, column decoders CD0, CD1, CD2,..., transfer transistors _Q00 , _Q01 , _Q02 ; _Q10 , _Q11 ,
Q ₁₂ ;... etc. are provided. Transfer transistors Q ₀₀ , Q ₀₁ , and Q ₀₂ are connected to the bit line BL, respectively.
0 and data buses DB-1, DB0, DB+1, and transfer transistors Q ₁₀ ,
Q ₁₁ and Q ₁₂ are bit line BL1 and data bus respectively
DB-1, DB0, and DB+1, and other transfer transistors are similarly connected between each bit line and each data bus. The output of each column decoder is sent to the gate of a transfer transistor connected between one bit line and data bus DB0, and to the bit lines located on both sides of the bit line and data buses DB-1 and DB+.
1 and the gates of the transfer transistors connected between the gates and the gates of the transfer transistors. For example, the output of column decoder CDS1 is applied to the gate of transfer transistor _Q11 connected between bit line BL1 and data bus DB0, and the gate of transfer transistor Q11 connected between bit line BL0 and data bus DB-1. It is commonly connected to the gate of transistor _Q00 and the gate of transfer transistor _Q22 connected between bit line BL2 and data bus DB+1. Note that each memory cell MC00, MC01,
... is a one-transistor, one-capacitor type, and one
The transfer transistor is composed of two capacitors and a transfer transistor that connects the capacitor to a corresponding bit line, and the transfer transistor is controlled by the potential of the corresponding word line. In the memory device shown in FIG. 18, for example, when the word line WL1 is selected and this potential is set to a high level, the memory cells connected to the word line WL1
The capacitors of MC01, MC11, MC21, MC31, ... correspond to the bit lines BL0 and BL, respectively.
Connected to 1, BL2, BL3,... For example, if memory cell MC11 is an addressable memory cell, by outputting a column selection signal from column decoder CD1, transfer transistor _Q11 and transfer transistor
Q ₀₀ and Q ₂₂ are turned on. As a result, in read mode, data in memory cell MC11 is transferred to bit line BL1 and transfer transistor.
Q ₁₁ is output via the data bus DB0, and is also output to the memory cells on both sides of the memory cell MC11.
The data of MC01 and MC21 are transferred to bit lines BL0 and BL2, transfer transistors _Q00 and _Q22 , and data buses DB-1 and DB, respectively.
+1. Therefore, by specifying the address of the center memory cell MC11,
By accessing MC11, memory cells MC adjacent to both sides of memory cell MC11 are simultaneously accessed.
It is also possible to access 01 and MC21, for example, to read data. However, in the semiconductor memory device of FIG. 18, only adjacent columns of the same word line can be read. In image processing, etc., data that is two-dimensionally spread is often required. For example, 3×3 spread areas (MC00, MC10, MC20), (MC01, MC
11, MC21), (MC02, MC12, MC2
When data 2) is required simultaneously, in the semiconductor memory device described above, selection of word line WL0, selection of column decoder CD1, selection of WL1 and selection of CD1, further selection of WL2 and selection of CD1 are performed.
A similar selection operation, such as the selection of , must be repeated three times, which leaves complexity in the memory access operation and does not sufficiently shorten the access time. FIG. 19 is also a block circuit diagram showing a conventional boundary-free semiconductor memory device, in which adjacent memory cells connected to adjacent word lines are simultaneously accessed in parallel to the accessed memory cell. It is. In Figure 19,
The entire chip is divided into first to fourth blocks 1 to 4. 6 is a data bus selection circuit, and 7 is a data bus. In addition, the first block 1 has data lines BL0 to BL4 and word lines WL0, WL4, WL
Memory cells MC00 to MC connected between
40, a cell block 11 consisting of MC04 to MC44, MC08 to MC48, a bit line selection circuit 12 in which transfer transistors are connected in the same manner as shown in FIG. 18, a row decoder 13 and its addition circuit 14. . 2nd to 4th
Blocks 2 to 4 are similarly constructed. However, the adder circuit 1 is installed in the second and third blocks 2 and 3.
On the other hand, the fourth block 4 is provided with a subtraction circuit 44 in place of the addition circuit 14. Further, column decoders 51 and 52 are connected to first and second blocks 1 and 2 and third and fourth cell blocks 3 and 4, respectively. 1st
~Bit line selection circuit 1 of fourth blocks 1 to 4
2, 22, 32, and 42 are connected to the data bus selection circuit 6 via data buses 71-74. Here, when considering only the random access operation, each block 1 to 4 operates completely in parallel in response to row address signals A ₂ to _{A 8} , and operates in parallel depending on the row address signals A ₀ and A ₁ of the lowest two bits. The data bus selection circuit 6 side determines which block is to be accessed. Therefore, if the word lines selected when the row address signals A ₀ to A ₈ are counted up one by one from 0 are WL ₀ , WL ₁ , ... WL _o , then in the first cell block 11, the word lines are WL0. ，
WL4, WL8,..., WL1, WL5, WL9,... in the second cell block 21, WL2, WL6, WL10,... in the third cell block 31, WL3, WL7, WL in the fourth cell block 41
As shown in 11, when viewed in address order, they are separated by 4 within each cell block, and adjacent ones, for example, WL0 and WL1, and WL1 and WL2, belong to different cell blocks and are provided in adjacent cell blocks. Within each block, word lines designated by adjacent row addresses are selected and operated simultaneously. Therefore, by outputting data to the memory cells of the selected word line in parallel in each block, the memory cells of adjacent row addresses can be accessed in parallel. However, when the center row address by random access selects the word line in either end blocks 1 or 4, the word line corresponding to the row address immediately before or after that row address is not selected. state. In other words, even if each block is simply operated in parallel, word line data related to a specific address cannot be output in parallel depending on the row address. Therefore, in a mode in which memory cells on adjacent word lines are simultaneously accessed, a contrivance has been taken to make the word line selection order cyclic for both end blocks. In addition, FIG. 19 shows a case where the memory cell is 256K, and a 9-bit address signal A0 to _A0 is used on the low side for addressing the memory cell.
A ₈ (A ₀ is LSD, A ₈ is MSD) is decoder circuit 1
3, 23, 33, and 43. however,
The decoder circuits 23 and 33 are connected only to the ₈ bits A ₂ to A, and the ₈ bits A' ₂ to A' processed by the adder circuit 14 for the ₈ bits A ₀ to A are applied to the decoder circuit 13. The decoder circuit 43 is applied with ₈ bits A″ ₂ to A″ processed by the subtraction circuit 44 . Furthermore, the A ₀ and A ₁ bits are applied to the data bus selection circuit 6. [Problems to be Solved by the Invention] However, in the boundary-free semiconductor memory device shown in FIG.
A 3x3 bit set is obtained by installing a subtraction circuit, etc. and a special decoder on the column side, but it is almost impossible to expand this to 4x4, 5x5, etc. bit sets. In addition, the column decoder must be arranged at the bit line pitch, that is, with the minimum transistor size, which leads to an increase in the length of the column decoder in the bit line direction, resulting in increased capacity and higher integration. spoil the situation. In addition, the column decoder is arranged at the same bit line pitch, and therefore, for example, wiring for the bit line and three transfer transistors must be done for each bit line pitch. In order to do this without reducing the performance, advanced multilayer wiring technology is required, which is still disadvantageous in terms of large capacity and high integration. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a boundary-free semiconductor memory device in which the shape of a bit aggregate to be accessed can be easily reduced and expanded without impairing the capacity and integration. [Means for solving the problem] A means for solving the above-mentioned problem is shown in FIG. In Figure 1, memory cells are arranged in n rows x
m columns of memory cell blocks B ₀₀ , B ₀₁ ,...,
B _0,n-1 ;B ₁₀ ,B ₁₁ ,…,B _1,n-1 ;…;B _o-1,0 ,
It is divided into B _o-1,1 , ..., B _o-1,n-1 . n identical row selection means RD are provided in common for each row of memory cell blocks, m identical column selection means
CD is provided commonly to the memory cell blocks of each column. Further, the first switch means RSW gives each row selection means the row address A _R or the row address A R +1 adjacent to the row address, and the second switch means CSW gives each column selection means the column address A _C or the row address A _R +1 adjacent to the row address A R +1. Give the column address A _C +1 next to the column address. The alignment means selects n×m of each memory cell block accessed by each row selection means and each column selection means.
Rearrange cells. This allows access to a desired rectangular bit collection. Note that A _R is a decimal address vector notation created from the upper (k-1og ₂ n) bits excluding the lower 1og ₂ n bits of the total number of bits k of the externally input row address, and similarly, , A _C is a decimal address vector notation made of the upper (-1og ₂ m) bits excluding the lower 1og ₂ m bits of the total number of bits of the column address input from the outside. [Operation] According to the above-described means, both the row decoder and the column decoder are constructed using a normal circuit technique.
In addition, the sorting means invalidates some cells when rearranging n×m cells, thereby allowing access to n′×m′ (n′≦n, m′≦m) bit aggregates. is possible. In other words, it is possible to reduce or enlarge the bit aggregate. [Example] First, boundary free will be explained with reference to FIG. In FIG. 2, a 1M bit bit map structure is shown. That is, 1024 memory cells are arranged along the X direction, and 1024 memory cells are arranged along the Y direction. In this case, one row is selected by a 10-bit row address RA0-RA9, and one column is selected by a 10-bit column address CA0-CA9. Here, we assume that a 4x4 rectangular bit collection is to be accessed at the same time, and in this case, the pointing bits PB are
By specifying and accessing, the neighboring bits (within the thick line frame) of the pointing bit PB will also be accessed. Any bit on the bit map is a pointing bit like this PB.
If this is possible, there is no boundary within the chip, that is, the chip is boundary-free. Also, when the pointing bit PB approaches the limit of the chip, a chip boundary exists. Therefore, in order to eliminate such chip boundaries, the boundaries are made circular. for example,
As shown in FIG. 3A, when the boundary exceeds the chip's low boundary, the area with a small row address is accessed at the same time, and as shown in FIG. 3B, when the boundary exceeds the chip's column boundary, Areas with small column addresses are accessed at the same time, and when the boundary exceeds both the low boundary and column boundary of the chip, as shown in Figure 3C, the areas with small column addresses are also accessed at the same time. I'll do what I do. As a result, a chip boundary-free semiconductor memory device can be obtained. The present invention relates to a semiconductor memory device which is both address boundary free within a chip and chip boundary free. FIG. 4 is a circuit diagram showing an embodiment of a semiconductor memory device (chip) according to the present invention. In Figure 4, there are 16 1M (1048576) bit memory cells.
It is divided into cell blocks B ₀₀ , B ₀₁ , ..., B ₃₃ . That is, each cell block B ₀₀ , B ₀₁ , ..., B ₃₃
is 64K (65536) bits. Here, the memory cell bitmap (see FIG. 2) is allocated to blocks as shown in FIG. One row decoder RD0 is provided in common for the four cell blocks B ₀₀ , B ₀₁ , B ₀₂ , and B ₀₃ , and one row decoder RD0 is provided in common for the four cell blocks B ₁₀ , B ₁₁ , B ₁₂ , and B ₁₃ . A decoder RD1 is provided in common, and four cell blocks B ₂₀ , B ₂₁ , B ₂₂ , B ₂₃
One row decoder RD2 is commonly provided for four cell blocks B ₃₀ , B ₃₁ , B ₃₂ ,
One row decoder RD3 is provided in common for _B33 . These low decoders RD0~
RD3 has the same configuration. On the other hand, one column decoder CD0 is provided in common for the four cell blocks B ₀₀ , B ₁₀ , B ₂₀ , and B ₃₀ , and one column decoder CD0 is provided in common for the four cell blocks B ₀₁ , B ₁₁ , B ₂₁ , and B ₃₁ . A column decoder CD1 is provided in common, and one column decoder CD2 is provided in common for four cell blocks B ₀₂ , B ₁₂ , B ₂₂ , B ₃₂ , and four cell blocks B ₀₃ , B ₁₃ , B ₂₃ , One column decoder CD3 is provided in common for _B33 . These column decoders CD0 to CD3 also have the same configuration. The upper 8 bits RA2 to RA9 of the 10-bit row address RA0 to RA9 are incrementers.
+1 (in decimal notation) is added by INR, and as a result, two addresses, +0 address (through) and +1 address (increment), are supplied to the low side switches RSW0 to RSW3. and,
These low-side switches RSW0 to RSW3 select the lower 2 bits of the 10-bit row address, RA0,
Two addresses, ie, +0 address and +1 address, are switched according to RA1 and supplied to each row decoder RD0 to RD3. On the other hand, of the 10-bit column address CA0-CA9, the upper 8 bits CA2-CA9 are incremented by the incrementer INC.
1 (in decimal notation) is added, resulting in +0 address (through) and +1 address (increment)
The two addresses are column side switch CSW0~
Supplied to CSW3. These column side switches CSW0 to CSW3 switch between two addresses, that is, +0 address and +1 address, according to the lower two bits CA0 and CA1 of the 10-bit column address, and each column decoder CD0
~Supply to CD3. However, in this case, as described later, each cell block has a configuration in which two bit lines are accessed, so the 1-bit output from the column side switches CSW0 to CSW3 is not sent to the column decoder but to the selector _S00. , S ₁₀ ,
S ₂₀ , S ₃₀ ;...; S ₃₀ , S ₃₁ , S ₃₂ , S ₃₃ . 16 selectors S ₀₀ , S ₁₀ , S ₂₀ , S ₃₀ ;...; S ₃₀ ,
S ₃₁ , S ₃₂ , S ₃₃ are block data buses BDB1,
It is connected to the bus alignment circuit BAC via BDB2. This bus alignment circuit BAC is the lower address RA
Selector S ₀₀ ~ according to 0, RA1, CA0, CA1
Controls the connection between _S33 and input/output terminals IO ₀ to _{IO 15} . Further, the control circuit CONT controls each section according to the chip enable signal, read/write signal R/W, etc. FIG. 6 is a detailed circuit diagram of the cell block _Bij of FIG. 4. In FIG. 6, a folded bit line is used. That is, as shown in the partial detail diagram of FIG. 7, memory cells are provided at every other intersection of a pair of bit lines and word lines connected to one side of each sense amplifier SA.
Note that the sense amplifier SA in FIG. 7 is composed of a P channel transistor cross-coupled between the line PSA and the bit line BL0,
It is composed of an N-channel transistor coupled between NSA and bit lines BL0,0, and operates when line PSA is at a high potential and line NSA is at a low potential. In addition, in FIG. 6, the row decoder RDi has 256 word lines WL _i,0 , WL _i,1 ,
..., WL _i,255 , column decoder CDj selects its column selection signal.
CD _j,0 , CD _j,1 , ..., CD _j,127 select two pairs of bit lines, for example BL0,0; BL1,1, and block data buses DB _ij,0 , _ij,0 , DB _{ij, 1} ,
DB _ij,1 , and these two pairs of intra-block data buses DB _ij,0 , _ij,0 , DB _ij,1 , _ij,1
Any one pair of data buses BDB ij _{and ij} is selected by a switch S ij and connected to the block data buses BDB _{ij and ij} . The switch S _ij has two data bus latches L0,
It is composed of L1 and two selectors SEL0 and SEL1, and each selector is composed of an inverter I, AND circuits _G1 and _G2 , and an OR circuit _G3 , as shown in FIG. That is, one of the data bus latches L0 and L1 corresponding to the 1-bit CSW _j of the column address is connected to the block data buses BDB _ij and _ij . According to the configuration of cell block _Bij shown in FIG.
Since each column decoder CD _j has a 128-bit configuration, it is useful for downsizing the column decoder and therefore for increasing capacity and integration. However, in the present invention, such a cell block configuration is merely an example. It's nothing more than that. In other words, it may be an open bit type. Also, each column decoder CD _j
Alternatively, one pair of bit lines may be directly selected from 256 pairs of bit lines. In this case, all 8-bit addresses from each column-side switch CSW0 to CSW3 are supplied to the corresponding column decoder CD _j , and switch S _ij is deleted. In Figure 4, the 4x4 shown in the thick line frame in Figure 5
When accessing a set of bits (the same in Figure 2), in order to set the pointing bit to the upper left corner, the bitmap X coordinate is (CA9, CA8,..., CA0) = (0000000011). As the Y coordinate, (RA9, RA8,..., RA0) = (0000000001) is given from the outside. That is, each cell block
The upper 16 bits of the address given to _Bij (RA9~
If RA2, CA9 to CA2) are the same, a 4×4 address boundary as shown by the thick line frame in FIG. 5 exists on the logical plane. At this time, in order to always access the 4 bits whose X coordinate (column) is larger than the pointing bit and the 4 bits whose Y coordinate (row) is larger than the pointing bit, the row decoders RD0 to
The upper 16 bits to be input to RD3 and column decoders CD0 to CD3 may be input separately as +0 (through) or +1 (increment).
In this way, the address boundary indicated by the thick line frame in FIG. 5 disappears. +0 (through) or +1 (increment) as described above
This case classification must be performed for each cell block _Bij , but for each row of cell blocks, for example,
B ₀₀ , B ₀₁ , B ₀₂ , B ₀₃ share the row decoder RD0, and the cell blocks of each column, for example, B ₀₀ , B ₁₀ ,
Since B ₂₀ and B ₃₀ share the column decoder CD0, eight low side switches RSW0 to RSW3
Only the column side switches CSW0 to CSW3 are required. As shown in Figure 9, each switch RSW0~
RSW3 (or CSW0 to CSW3) is the lower 2 bits of the row (or column) address RA
Decoder DEC1 that decodes 0, RA1 (or CA0, CA1) and the output of decoder DEC1
8-bit selector SEL that operates according to SWT
It consists of. Here, the decoder DEC1 is a circuit whose decoding logic differs depending on each switch and satisfies the logical formula shown in Table 1. Table 1 Switches SWT RSW0 (RA0) + (RA1) RSW1 (RA1) RSW2 (RA0)・(RA1) RSW3 φ CSW0 (CA0) + (CA1) CSW1 (CA1) CSW2 (CA0)・(CA1) CSW3 φ Here In this case, the logical formula for the row side switch and the logical formula for the column side switch match because the bit aggregate has the same width in the row direction and the width in the column direction, but the bit aggregate is 2×8, 3× If the width in the row direction and the width in the column direction are different, as in the case of 5, . . . The logical formulas in Table 1 are illustrated by FIG.
Here, FIG. 10 is a diagram showing the row address boundary, and the three thick lines in the horizontal direction are the row address boundaries defined by the upper eight bits RA9 to RA2 of the row address. Here, 4 blocks B _0J ,
B _1j , B _2j , and B _3j have a difference in the lower two bits of the Y coordinate (low) of the bitmap plane. The format of the 4×4 bit aggregate to be accessed is as follows:
, , there are four ways. In the case of form,
Since the row address boundary is not crossed, the same external addresses RA9 to RA2 are supplied as is (through) to each cell block B _0j , B _1j , B _2j , and B _3j . In the case of the form, only the row address of cell block B _0j is incremented by 1; in the case of the form, cell block B _0j ,
Each row address of B _1j is incremented by 1, and in the case of the cell block B _0j , B _1j ,
B _2j Increment each row address by 1. If you organize this, it will look like Table 2.

[Table] The first table is a logical expression of this second table using the lower two bits RA1 and RA0 of the row address indicating the pointing bit position. Note that the same applies to the column address side. In this way, a boundary-free 4 x 4 bit aggregate can be accessed from the bit map, for example, data can be read out. However, if the data is read out to the input/output terminals IO ₀ to IO ₁₅ as it is, it will be processed in the vicinity of the image data. is inconvenient. for example,
When the 4×4 bit collection corresponding to the block shown in FIG. 11A is read out without alignment, it becomes as shown in FIG. 11B, where the pointing bit on the bit map and other neighboring bits are 4× The logical relationships among the four shapes are not maintained, and as a result, 4×4 surface access differs from location to location. Actually, an input/output terminal arrangement as shown in FIG. 11C is desired. In other words, 1 pointing bit PB is always an input/output terminal.
IO ₀ is accessed. 2 The 4 bits at positions incremented in the X direction from pointing bit PB are
Accessed in the order of IO ₀ , IO ₁ , IO ₂ , and IO ₃ . 3 Then, it is incremented in the Y direction, and similarly to 2), the 4 bits at the incremented positions in the X direction are IO ₄ , IO ₅ , IO ₆ , IO ₇
accessed in this order. Regardless of the pointing bit PB address, the IO shown in Figure 11C is always read from the bit map.
A bus alignment circuit BAC is provided for accessing the 4×4 bit collections in correspondence. As shown in detail in FIG. 12, the bus alignment circuit BAC has a block data bus BDB _ij connected to a cell block B _ij that has 16 input/output terminals IO ₀ to IO _{15 .}
It has a demultiplexer circuit DMPX (actually, 16 demultiplexers) that operates so as to be connected to one of the demultiplexers DMPX, and a decoder DEC2 that controls each demultiplexer of the demultiplexer circuit DMPX. In this case, decoder DEC2 is low and the lower 4 bits of column address RA1, RA0, CA
1. Demultiplexer circuit DMPX according to CA0
control. In addition, the demultiplexer circuit
The AND circuit in the DMPX is composed of, for example, a CMOS switch shown in FIG. The bus alignment circuit BAC configured in this manner connects the bus block _Bij and the input/output terminal _IOk in accordance with the correspondence shown in Table 3.

【table】

〔Effect of the invention〕

As explained above, according to the present invention, the access can be expanded to access bit aggregates of any size, and since a normal decoder can be used, there is no need to sacrifice large capacity or high integration. Therefore, a boundary-free semiconductor memory device can be obtained.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a diagram showing a bitmap configuration, FIGS. 3A to 3C are diagrams explaining boundary free, and FIG. 4 is an implementation of a semiconductor memory device according to the present invention. A block circuit diagram showing an example; FIG. 5 is a diagram showing block allocation of a bitmap according to the present invention; FIG. 6 is a detailed circuit diagram of the cell block of FIG. 4; FIG. 7 is a partial detailed diagram of FIG. 6; Figure 8 is a detailed circuit diagram of the selector in Figure 6,
9 is a detailed circuit diagram of the row side switch (column side switch) in FIG. 4, FIG. 10 is a diagram explaining the row address boundary, FIG. 11 is a diagram showing the cell block data in FIG. Figure 12 is a detailed circuit diagram of the bus alignment circuit in Figure 4, and Figure 13 is a detailed circuit diagram of the bus alignment circuit in Figure 4.
14 is a diagram explaining the position of the pointing bit, FIGS. 15 and 16 are circuit diagrams showing an internal address calculation circuit added to FIG. 4, and FIG. 17 is a circuit diagram of the conventional 18 and 19 are block circuit diagrams showing a conventional boundary-free semiconductor memory device. FIGS. B ₀₀ , B ₀₁ , ...Cell block, RD0 to RD3
...Low decoder, CD0~CD3...Column decoder, RSW0~RSW3...Low side switch,
CSW0~CSW3...Column side switch, BAC...
...Bus alignment circuit.

Claims (1)

[Claims] 1 Memory cell block (B ₀₀ ,
B ₀₁ ,…, B _0,n-1 ;B ₁₀ ,B ₁₁ ,…,B _1,n-1 ;…;
B _o-1,0 , B _o-1,1 , ..., B _o-1,n-1 ), n identical row selection means RD provided in common to the memory cell blocks of each row, m identical column selection means CD commonly provided in the memory cell blocks of each column, and a row address A _R or a row address adjacent to the row address (A _R +1) for each row selection means.
a first switch means RSW for giving a column address A _C or a column address (A _C +1) next to the column address to each of the column selection means; n×m of each memory cell block accessed by each column selection means
What is claimed is: 1. A semiconductor memory device comprising: alignment means for realigning individual cells; and enabling access to a desired rectangular bit aggregate.