JP2590704B2 - Parallel processor LSI - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access system, and more particularly to a memory access system used for a parallel processor LSI.

[0002]

2. Description of the Related Art Decoders in all memory blocks constituting a highly integrated memory are connected to a common address bus. FIG. 1 shows the configuration of an LSI in which this highly integrated memory and a plurality of processors are integrated. FIG.
1 is a block diagram of a parallel processor LSI including a plurality of processors 1, a plurality of memory blocks 2, and a main word decoder 3. FIG. Here, when a parallel processor is used, selection of memory blocks is stopped, and all memory blocks are simultaneously selected, so that all PEs can simultaneously access the memory blocks. The main word decoder 3 is connected to the section word decoders 22 of all the memory blocks 2 via the main word line 32. The main word decoder 3 is connected to an external address line A for inputting an external address which is a part of the external address from outside the chip.
The main word decoder 3 supplies the result of decoding the given address to all section word decoders. As a result, one area is selected when the memory cell array is divided into areas corresponding to the number of main word lines 32. Further, of the external addresses, an address given via an external address line B41 for inputting a part other than the part assigned to the external address line A is decoded by the section word decoder 22 and the column decoder 23, and The address in the area selected by the output signal is determined. Based on the address determined in this way, a memory access is performed from a corresponding processor for each memory block.

[0003]

In the configuration described above, the same address is given to all section word decoders and column decoders via a common address bus. In such a method in which memory access is made to all memory blocks with a common address, in an algorithm in which each processor needs to access a different address, parallel memory access cannot be performed, and high performance cannot be obtained. There was a problem.

[0004]

SUMMARY OF THE INVENTION A parallel processor LSI of the present invention is an LSI for integrating a plurality of processors and a highly integrated memory, and each memory block corresponds to every memory block constituting the highly integrated memory. To have a processor. The input signal line of the decoder in each memory block is connected to the output signal line of the corresponding processor.

[0005]

FIG. 2 shows a parallel processor LSI according to the present invention.
FIG. 3 is a block diagram showing one embodiment of the present invention.

FIG. 2 includes a plurality of processors 1 and a plurality of memory blocks 2 connected to a main word decoder 3. The processor 1 and the memory block 2 are connected by an address line 42 and a data line 43. Processor 1
Has an operation unit 11 and an index register 12. The operation unit 11 performs an operation with reference to the contents of the index register 12, and writes the operation result to the index register 12. The memory block 2 includes a memory cell 21, a section word decoder 22, and a column decoder 23. The address line 43 is connected to the section word decoder 22.
And the column decoder 23. The contents of the index register 12 are input to the section word decoder 22 and the column decoder 23 via the address line 43 as an address.

In this parallel processor LSI, when a parallel memory access instruction is issued, a memory area at the same relative address is selected for all memory cell arrays by the external address A31 input to the main word decoder 3. At this time, data is read from the memory cell 21 via the data line 42 when a memory read command is issued, and data is written when a memory write command is issued. Since the same operation is performed on the memory blocks 2 from all the processors 1 arranged in the horizontal direction, it is possible to access the corresponding memory blocks with different addresses for each processor.

In FIG. 2, the address given from the processor 1 is fixed to the index register 12. However, if the register file 60 is provided as shown in FIG. 3, one register can be selected from a plurality of registers and used as an address. it can. When there is only an index register, after performing a certain memory access, it is necessary to perform an address calculation for the next memory access, and it is necessary to alternately perform the memory access and the address calculation. Then, some addresses are calculated in advance by the arithmetic unit 11 and the registers in the register file 60, the results are stored in a plurality of registers, and the registers used as the addresses in the area at the time of the memory access instruction are sequentially set. It is also possible to perform access while switching.

By providing a selector 70 between the processor and the memory block as shown in FIG. 4, it is possible to select an externally applied address and an address from the processor by the address bus 5. As a result, it is possible to select whether to access all memory blocks using a common address or to access each memory block using an individual address.

[0010]

As described above, in the conventional parallel processor LSI, all memory blocks can be accessed only by the same address. However, in the present invention, the operation result of each processor is used as an address for each memory block. Can be accessed at different addresses. Also, the present invention makes only a small circuit change to the configuration of the highly integrated memory, which only requires changing the input line to the decoder.
It can be realized at low cost without reducing the degree of integration of the highly integrated memory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a conventional parallel processor LSI.

FIG. 2 is a parallel processor LSI according to one embodiment of the present invention;
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 3 is a block diagram showing another embodiment of a processor unit.

FIG. 4 is a block diagram showing another embodiment of an address line connection between a processor and a memory block.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processor 11 Operation unit 12 Index register 2 Memory block 21 Memory cell 22 Section word decoder 23 Column decoder 3 Main word decoder 41 External address line B 42 Data line 43 Address line 5 Address bus 60 Register file 70 Selector 221 Section word line 31 External Address line A 32 Main word line

Claims (1)

(57) [Claims] 1. An LSI for integrating a plurality of processors and a highly integrated memory, wherein each memory block has a corresponding processor for all memory blocks constituting the highly integrated memory, and a decoder in each memory block. Wherein the input signal lines are connected to the output signal lines of the corresponding processors, respectively.