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JPS5793548A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5793548A
JPS5793548A JP17039580A JP17039580A JPS5793548A JP S5793548 A JPS5793548 A JP S5793548A JP 17039580 A JP17039580 A JP 17039580A JP 17039580 A JP17039580 A JP 17039580A JP S5793548 A JPS5793548 A JP S5793548A
Authority
JP
Japan
Prior art keywords
window
psg film
layers
reduced pressure
pressure cvd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17039580A
Other languages
Japanese (ja)
Other versions
JPS6160580B2 (en
Inventor
Kazunori Imaoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17039580A priority Critical patent/JPS5793548A/en
Publication of JPS5793548A publication Critical patent/JPS5793548A/en
Publication of JPS6160580B2 publication Critical patent/JPS6160580B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To eliminate the damage of the junction of a functional region under an electrode window when a wiring is alloyed by eliminating the stepwise difference of the window by a connecting method of the functional region with the wire and preventing the disconnection of the metallic wiring. CONSTITUTION:An electrode window 16 for exposing a source and drain region 13 is formed at the PSG film 15 being formed on a semiconductor substrate 14 by dry etching. Subsequently, the first polysilicon layer 18 containing phosphorus is formed by a reduced pressure CVD method, and the second polysilicon layer 19 containing no impurity is formed by a reduced pressure CVD method thereon. The layer 18, 19 formed on the PSG film are removed by a plasma etching method, and an aluminum wire 20 contacted with the layers 18, 19 is formed on the PSG film flatly buried with the layers 18, 19 with the window to the upper surface on the substrate.
JP17039580A 1980-12-03 1980-12-03 Manufacture of semiconductor device Granted JPS5793548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17039580A JPS5793548A (en) 1980-12-03 1980-12-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17039580A JPS5793548A (en) 1980-12-03 1980-12-03 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5793548A true JPS5793548A (en) 1982-06-10
JPS6160580B2 JPS6160580B2 (en) 1986-12-22

Family

ID=15904125

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17039580A Granted JPS5793548A (en) 1980-12-03 1980-12-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5793548A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6110256A (en) * 1984-06-14 1986-01-17 コミツサレ・ア・レナジイ・アトミツク Method of automatically positioning mutual connection line to connecting hole of integrated circuit
JPS62217636A (en) * 1986-03-19 1987-09-25 Fujitsu Ltd Manufacturing method of semiconductor device
US5093275A (en) * 1989-09-22 1992-03-03 The Board Of Regents, The University Of Texas System Method for forming hot-carrier suppressed sub-micron MISFET device
US5234863A (en) * 1990-12-11 1993-08-10 Seiko Instruments Inc. Method of manufacturing doped contacts to semiconductor devices

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6110256A (en) * 1984-06-14 1986-01-17 コミツサレ・ア・レナジイ・アトミツク Method of automatically positioning mutual connection line to connecting hole of integrated circuit
JPS62217636A (en) * 1986-03-19 1987-09-25 Fujitsu Ltd Manufacturing method of semiconductor device
US5093275A (en) * 1989-09-22 1992-03-03 The Board Of Regents, The University Of Texas System Method for forming hot-carrier suppressed sub-micron MISFET device
US5234863A (en) * 1990-12-11 1993-08-10 Seiko Instruments Inc. Method of manufacturing doped contacts to semiconductor devices

Also Published As

Publication number Publication date
JPS6160580B2 (en) 1986-12-22

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