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JPS5583264A - Method of fabricating mos semiconductor device - Google Patents

Method of fabricating mos semiconductor device

Info

Publication number
JPS5583264A
JPS5583264A JP15835278A JP15835278A JPS5583264A JP S5583264 A JPS5583264 A JP S5583264A JP 15835278 A JP15835278 A JP 15835278A JP 15835278 A JP15835278 A JP 15835278A JP S5583264 A JPS5583264 A JP S5583264A
Authority
JP
Japan
Prior art keywords
source
layer
substrate
region
entire surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15835278A
Other languages
Japanese (ja)
Inventor
Hitoshi Takahashi
Katsumi Nishimura
Tsuyoshi Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15835278A priority Critical patent/JPS5583264A/en
Publication of JPS5583264A publication Critical patent/JPS5583264A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To lead out a source electrode from a semiconductor substrate by forming source and drain regions in the substrate, coating a reaction preventive film on the entire surface thereof, perforating an opening only in the source region, coating an aluminum film thereon, and producing alloy communicating with the substrate in the source region.
CONSTITUTION: A p-type layer 11 is epitaxially grown on a p+-type semiconductor substrate 10, thick isolation SiO2 layers 12 are formed at both ends thereof, and gate oxide film and gate polycrystalline silicon electrode 13 are formed on the substrate 10 surrounded by the layer 12. Then, a PSG layer 14 is coated on the entire surface containing the source and drain forming regions exposed at both sides, and heat treated to thereby form n+-type source and drain regions 15 and 16. Then, an electrode contacting opening is perforated only on the region 15, an n-type polycrystalline silicon layer 17 becoming a reaction preventive film is accumulated on the entire surface thereof, the portion over the contacting opening is removed, and an aluminum layer 18 is coated on the entire surface thereof to make contact with the region 15 through the opening. Then, it is heat treated to thereby occur an alloying reaction on the bonded surface of the region 15 to thus directly connect it to the layer 11 and to lead out the source electrode from the back surface of the substrate 10.
COPYRIGHT: (C)1980,JPO&Japio
JP15835278A 1978-12-19 1978-12-19 Method of fabricating mos semiconductor device Pending JPS5583264A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15835278A JPS5583264A (en) 1978-12-19 1978-12-19 Method of fabricating mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15835278A JPS5583264A (en) 1978-12-19 1978-12-19 Method of fabricating mos semiconductor device

Publications (1)

Publication Number Publication Date
JPS5583264A true JPS5583264A (en) 1980-06-23

Family

ID=15669768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15835278A Pending JPS5583264A (en) 1978-12-19 1978-12-19 Method of fabricating mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS5583264A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57162457A (en) * 1981-03-31 1982-10-06 Fujitsu Ltd Semiconductor memory unit
US5093276A (en) * 1984-12-11 1992-03-03 Seiko Epson Corporation Semiconductor device and method of production
US5190886A (en) * 1984-12-11 1993-03-02 Seiko Epson Corporation Semiconductor device and method of production
US5264721A (en) * 1989-04-29 1993-11-23 Fujitsu Limited Insulated-gate FET on an SOI-structure
US6130463A (en) * 1999-02-01 2000-10-10 Mitsubishi Denki Kabushiki Kaisha Field effect transistor and method of manufacturing same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57162457A (en) * 1981-03-31 1982-10-06 Fujitsu Ltd Semiconductor memory unit
US5093276A (en) * 1984-12-11 1992-03-03 Seiko Epson Corporation Semiconductor device and method of production
US5190886A (en) * 1984-12-11 1993-03-02 Seiko Epson Corporation Semiconductor device and method of production
US5264721A (en) * 1989-04-29 1993-11-23 Fujitsu Limited Insulated-gate FET on an SOI-structure
US6130463A (en) * 1999-02-01 2000-10-10 Mitsubishi Denki Kabushiki Kaisha Field effect transistor and method of manufacturing same
US6475844B1 (en) * 1999-02-01 2002-11-05 Mitsubishi Denki Kabushiki Kaisha Field effect transistor and method of manufacturing same

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