JPS5785128A - Multiplexer channel - Google Patents
Multiplexer channelInfo
- Publication number
- JPS5785128A JPS5785128A JP16166880A JP16166880A JPS5785128A JP S5785128 A JPS5785128 A JP S5785128A JP 16166880 A JP16166880 A JP 16166880A JP 16166880 A JP16166880 A JP 16166880A JP S5785128 A JPS5785128 A JP S5785128A
- Authority
- JP
- Japan
- Prior art keywords
- input
- transfer control
- output
- circuit
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To realize not only a multiplexer channel function but a selector channel function, by adding a block transfer control circuit to perform the block data transfer control between the own device and an input/output device. CONSTITUTION:When a block transfer start command is delivered to a block transfer control circuit 230 from an ROM218, a status request signal is produced and sent to an input/output device 113. The device 113 connected to a multiplexer channel 116 answers to the status request signal by a connection action the input and output devices through an input/output bus control circuit 221 and then transmits the status data to the circuit 230. Thus the state of the circuit 230 is not changed when the device 113 is busy. When the device 113 is set in the ready state, the data corresponding within a lead buffer register 210 is transmitted onto an input/output bus 112. After this, the data transfer of each byte is repeated without switching the input and output devices. In such a way, the data transfer control is also made possible in the selector mode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16166880A JPS5785128A (en) | 1980-11-17 | 1980-11-17 | Multiplexer channel |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16166880A JPS5785128A (en) | 1980-11-17 | 1980-11-17 | Multiplexer channel |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5785128A true JPS5785128A (en) | 1982-05-27 |
Family
ID=15739560
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16166880A Pending JPS5785128A (en) | 1980-11-17 | 1980-11-17 | Multiplexer channel |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5785128A (en) |
-
1980
- 1980-11-17 JP JP16166880A patent/JPS5785128A/en active Pending
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