JPS5758299A - Read only memory circuit - Google Patents
Read only memory circuitInfo
- Publication number
- JPS5758299A JPS5758299A JP13210680A JP13210680A JPS5758299A JP S5758299 A JPS5758299 A JP S5758299A JP 13210680 A JP13210680 A JP 13210680A JP 13210680 A JP13210680 A JP 13210680A JP S5758299 A JPS5758299 A JP S5758299A
- Authority
- JP
- Japan
- Prior art keywords
- output
- turns
- line
- load
- changes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
Abstract
PURPOSE:To enable high speed operation with low power consumption, by constituting the load with a parallel circuit of FETs having different gm. CONSTITUTION:A load L is constituted with a parallel circuit of an FET-Q1 which is of P channel type reverse to an MISFET-T for memory and has comparatively smaller gm and a Q2 which is of the same type at the Q1 and has comparatively greater gm. The Q1 is turned on with the power source line V2 at all times, and when the signal on an address line A is at ''1'', the T in a cell M turns on, the output of a bit line B is at ''0'', the output of an inverter 1 is at ''1'' and the Q2 turns off. When the address signal is at ''0'', the T turns off, and the output of the line B changes from ''0'' to ''1''. In this case, the output of the circuit 1 changes from ''1'' to ''0'', the Q2 turns on and the output of the line B becomes ''1'' rapidly.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13210680A JPS5758299A (en) | 1980-09-22 | 1980-09-22 | Read only memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13210680A JPS5758299A (en) | 1980-09-22 | 1980-09-22 | Read only memory circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5758299A true JPS5758299A (en) | 1982-04-07 |
Family
ID=15073582
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13210680A Pending JPS5758299A (en) | 1980-09-22 | 1980-09-22 | Read only memory circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5758299A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62170097A (en) * | 1986-01-21 | 1987-07-27 | Fujitsu Ltd | semiconductor storage device |
-
1980
- 1980-09-22 JP JP13210680A patent/JPS5758299A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62170097A (en) * | 1986-01-21 | 1987-07-27 | Fujitsu Ltd | semiconductor storage device |
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