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JPS5746371A - Cash storage device - Google Patents

Cash storage device

Info

Publication number
JPS5746371A
JPS5746371A JP55122722A JP12272280A JPS5746371A JP S5746371 A JPS5746371 A JP S5746371A JP 55122722 A JP55122722 A JP 55122722A JP 12272280 A JP12272280 A JP 12272280A JP S5746371 A JPS5746371 A JP S5746371A
Authority
JP
Japan
Prior art keywords
cash storage
boat
controller
storage device
storage via
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55122722A
Other languages
Japanese (ja)
Inventor
Masatoshi Tominaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55122722A priority Critical patent/JPS5746371A/en
Publication of JPS5746371A publication Critical patent/JPS5746371A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To realize not only the guaranty of dissidence but a high speed fot the cash storage, by adding the command accepting boat from a channel controller and the access boat to a storage device to the cash storage. CONSTITUTION:A high-speed channel controller 305 is connected to a cash storage via boats 307-310 within a system controller 301. A cash storage device 303 is connected to the cash storage via boats 311 and 313 within the controller 301. A multiplexer channel device 306 is connected to the cash storage via a boat 312 within the controller 301. Furthermore a local memory 302 is connected to the cash storage via a boat 318 within the device 303; and an input/output processor 304 is connected to the cash storage via a boat 317.
JP55122722A 1980-09-04 1980-09-04 Cash storage device Pending JPS5746371A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55122722A JPS5746371A (en) 1980-09-04 1980-09-04 Cash storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55122722A JPS5746371A (en) 1980-09-04 1980-09-04 Cash storage device

Publications (1)

Publication Number Publication Date
JPS5746371A true JPS5746371A (en) 1982-03-16

Family

ID=14842963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55122722A Pending JPS5746371A (en) 1980-09-04 1980-09-04 Cash storage device

Country Status (1)

Country Link
JP (1) JPS5746371A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62196749A (en) * 1986-02-22 1987-08-31 Hitachi Ltd Buffer memory controlling system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS556685A (en) * 1978-06-30 1980-01-18 Fujitsu Ltd Intermediate buffer memory control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS556685A (en) * 1978-06-30 1980-01-18 Fujitsu Ltd Intermediate buffer memory control system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62196749A (en) * 1986-02-22 1987-08-31 Hitachi Ltd Buffer memory controlling system
JPH0560619B2 (en) * 1986-02-22 1993-09-02 Hitachi Ltd

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