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JPS5731140A - Etching method by reactive ion - Google Patents

Etching method by reactive ion

Info

Publication number
JPS5731140A
JPS5731140A JP10576780A JP10576780A JPS5731140A JP S5731140 A JPS5731140 A JP S5731140A JP 10576780 A JP10576780 A JP 10576780A JP 10576780 A JP10576780 A JP 10576780A JP S5731140 A JPS5731140 A JP S5731140A
Authority
JP
Japan
Prior art keywords
frequency power
film
cf3br
poly
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10576780A
Other languages
Japanese (ja)
Inventor
Yukio Takeuchi
Masahiro Shibagaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10576780A priority Critical patent/JPS5731140A/en
Publication of JPS5731140A publication Critical patent/JPS5731140A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To etch a laminate of poly Si and a metallic silicide with the high melting point excellently by reactive ions by covering a parallel electrode plate at the side applying high-frequency power with a substance containing C and using a fixed mixed gas of CF3 and halongen. CONSTITUTION:Negative pole 5 between parallel electrodes 4, 5, is fixed to a turntable 7 to which a cooling pipe 6 is fitted, and the whole circumferential surface is coated with a polyester film 9. The high-frequency power is applied to the electrode 5 through the table 7. SiO222, poly Si 231, P-doped MoSi2232 and a resist mask 24 are stacked on a Si substrate 21 and used as a sample 25, and placed on a film 9. The mixed gas of CF3Br and Cl2 is introduced 2 and discharged 3, etching pressure is set to 0.1 Torr and the pressure rate of CF3Br to 2-10%, while 200W high-frequency power is applied and the film 23 is etched by reactive ions. According to this constitution, the etching follows presicely to a mask 24, a scar is not formed and a high accuracy pattern 23' with a steep side surface is obtained.
JP10576780A 1980-07-31 1980-07-31 Etching method by reactive ion Pending JPS5731140A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10576780A JPS5731140A (en) 1980-07-31 1980-07-31 Etching method by reactive ion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10576780A JPS5731140A (en) 1980-07-31 1980-07-31 Etching method by reactive ion

Publications (1)

Publication Number Publication Date
JPS5731140A true JPS5731140A (en) 1982-02-19

Family

ID=14416326

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10576780A Pending JPS5731140A (en) 1980-07-31 1980-07-31 Etching method by reactive ion

Country Status (1)

Country Link
JP (1) JPS5731140A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0094528A2 (en) * 1982-05-05 1983-11-23 Siemens Aktiengesellschaft Process for producing double-layer structures consisting of metal silicide and polysilicium on substrates containing integrated circuits by reactive ion etching
JPS5967635A (en) * 1982-07-06 1984-04-17 テキサス・インスツルメンツ・インコ−ポレイテツド Chemical composition for plasma etching for anisotropic etc-hing of silicon
JPS59181620A (en) * 1983-03-31 1984-10-16 Toshiba Corp Reactive-ion etching method
US4698126A (en) * 1985-03-18 1987-10-06 U.S. Philips Corporation Method of manufacturing a semiconductor device by plasma etching of a double layer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5414679A (en) * 1977-07-06 1979-02-03 Hitachi Ltd Plasma etching device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5414679A (en) * 1977-07-06 1979-02-03 Hitachi Ltd Plasma etching device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0094528A2 (en) * 1982-05-05 1983-11-23 Siemens Aktiengesellschaft Process for producing double-layer structures consisting of metal silicide and polysilicium on substrates containing integrated circuits by reactive ion etching
JPS58204538A (en) * 1982-05-05 1983-11-29 シ−メンス・アクチエンゲゼルシヤフト Method of fabricating metal silicide-polysilicon bilayer structures on substrates containing integrated circuits
JPS5967635A (en) * 1982-07-06 1984-04-17 テキサス・インスツルメンツ・インコ−ポレイテツド Chemical composition for plasma etching for anisotropic etc-hing of silicon
JPS59181620A (en) * 1983-03-31 1984-10-16 Toshiba Corp Reactive-ion etching method
US4698126A (en) * 1985-03-18 1987-10-06 U.S. Philips Corporation Method of manufacturing a semiconductor device by plasma etching of a double layer

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