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JPS58204538A - Method of fabricating metal silicide-polysilicon bilayer structures on substrates containing integrated circuits - Google Patents

Method of fabricating metal silicide-polysilicon bilayer structures on substrates containing integrated circuits

Info

Publication number
JPS58204538A
JPS58204538A JP58078103A JP7810383A JPS58204538A JP S58204538 A JPS58204538 A JP S58204538A JP 58078103 A JP58078103 A JP 58078103A JP 7810383 A JP7810383 A JP 7810383A JP S58204538 A JPS58204538 A JP S58204538A
Authority
JP
Japan
Prior art keywords
gas
chlorine
reactor
layer
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58078103A
Other languages
Japanese (ja)
Inventor
ウイリ−・バインフオ−ゲル
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Schuckertwerke AG
Siemens Corp
Original Assignee
Siemens Schuckertwerke AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Schuckertwerke AG, Siemens Corp filed Critical Siemens Schuckertwerke AG
Publication of JPS58204538A publication Critical patent/JPS58204538A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明は、集積半導体回路を含む/リコン基板上の金
属ケイ化物とポリシリコンから成る二重層に反応性のイ
オンエツチングにより構造を作る方法に関するものであ
る。シリコン基板は多くの場合絶縁膜で覆われている方
が有利であり、それを平板形の反応器に入れ、ホトマス
クで憶い・・ロゲ/を含む混合ガスを使用して反応性の
イオンエツチングを行なう。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for creating structures by reactive ion etching in bilayers of metal silicide and polysilicon on silicon substrates containing integrated semiconductor circuits. In many cases, it is advantageous for the silicon substrate to be covered with an insulating film, and it is placed in a flat plate reactor and etched using a photomask. Do the following.

金属ケイ化物は高度集積MO8回路の製造に際して次第
に重要性を増して来た。可能な使用分野はポリノリコン
ゲート技術において導体路とゲートの低抵抗材料として
である。この場合ポリシリコンは一般にケイ化物によっ
て置き換えられるのではなく、ドープされたポリシリコ
ン層上にケイ化物を置くという形でケイ化物が追加され
る。このような二重層に微細構造を作ることは、集積回
路の製作に際しては一連の境界φ件を考慮しなければな
らないことを考えると複雑なエツチング工程となる。
Metal silicides have become increasingly important in the fabrication of highly integrated MO8 circuits. A possible field of use is as a low-resistance material for conductor tracks and gates in polysilicon gate technology. In this case, the polysilicon is generally not replaced by silicide, but silicide is added by placing the silicide on a layer of doped polysilicon. Creating microstructures in such double layers is a complex etching process given that a series of boundary φ conditions must be considered in the fabrication of integrated circuits.

このようなエツチングの問題を解決することがこの発明
の目的である。
It is an object of the present invention to solve such etching problems.

集積回路を製作する際のエツチング過程において考1)
ハしなければならない境界条件を第1図によって詳細(
で説明する。ここで1はシリコン基板、2は基板表面の
5i021曽、3はn+型ドープのポリシリコン層% 
4はケイ化物層、5はエツチングマスクとなる感光樹脂
層、6は第1ボリンリコンゲイ−) 、。
Consideration 1) in the etching process when manufacturing integrated circuits
Figure 1 shows the boundary conditions that must be met in detail (
I will explain. Here, 1 is the silicon substrate, 2 is 5i021 on the substrate surface, and 3 is the n+ type doped polysilicon layer%.
4 is a silicide layer, 5 is a photosensitive resin layer serving as an etching mask, and 6 is a first boron silicone layer.

一ト、7はゲート上の酸化物絶縁層である。以下の南面
においてもこれらの番号はいずれも対応した部分を示し
ている、1第1図に記入されている垂直の矢印はいずれ
もこの発明が解決しようとしている問題があるエツチン
グl1liである。
1, 7 is an oxide insulating layer on the gate. In the south side below, all of these numbers indicate corresponding parts.1 The vertical arrows drawn in FIG.

矢印10では5i02又はそれに類する絶縁(オ料に7
1シて高度の選択性が要求される。二重層3゜4と51
02層2の厚さの比は20:1にまで達する。
At arrow 10, 5i02 or similar insulation (7
First, a high degree of selectivity is required. Double layer 3゜4 and 51
The thickness ratio of 02 layer 2 reaches up to 20:1.

矢印■1でilt蝕刻構造の縁端部に適箔な形状が要求
される。異方性エツチングにより図に示すような垂直端
面とするかあるいは傾斜エツチングにより傾斜面とする
As indicated by arrow (1), a suitable shape is required at the edge of the ilt etching structure. Vertical end faces as shown in the figure are formed by anisotropic etching, or inclined surfaces are formed by inclined etching.

矢印12では二重ポリンリコンゲート技術((おいて第
1ポリシリコンゲートの縁端の蝕刻残留物による短絡発
生の危険を避けるための段落の問題がある。
At arrow 12 there is a problem with double polysilicon gate technology (in order to avoid the risk of short circuits caused by etching residues on the edge of the first polysilicon gate).

矢印1:3では基板1に対する二重層3,4の接触即ら
埋込み接触の形成の問題がある。
At arrow 1:3 there is the problem of forming a contact or a buried contact of the double layer 3, 4 to the substrate 1.

これらの問題の解決の外にこの発明にはエツチング過程
において侵されることのない感光樹脂マスクをエツチン
グマスクとしてf吏用されるように  。
In addition to solving these problems, the present invention includes the use of a photosensitive resin mask as an etching mask, which is not attacked during the etching process.

するという目的がある。更に短チヤネル効果と呼ばれた
いる現象を考!ばして総ての部分において高度の腐蝕均
等性が必要である。
There is a purpose to do so. Furthermore, consider a phenomenon called the short channel effect! Furthermore, a high degree of corrosion uniformity is required in all parts.

はとんど総ての場合においてモリブデンおよびタングス
テンのケイ化物である多結晶ケイ化物の構造に対する蝕
刻方法は既に公知である。しかしモリブデンとタングス
テンのケイ化物よりも高温度においての耐熱性が高く、
ポリシリコンに対する接着性が良い点で著しく有利なケ
イ化タンタル構造のエツチングに関しては文献(J、 
Vac、Sci。
Etching methods for polycrystalline silicide structures, which in most cases are silicides of molybdenum and tungsten, are already known. However, it has higher heat resistance at high temperatures than molybdenum and tungsten silicides,
Regarding the etching of tantalum silicide structures, which are extremely advantageous in terms of good adhesion to polysilicon, the literature (J.
Vac, Sci.

Technol、 1.7.  (4)  July/
Aug、 l 980. p。
Technol, 1.7. (4) July/
Aug, l 980. p.

787〜788)に簡単に言及されているだけである。787-788).

それによればチタン、タンタル、モリブデンおよびタン
グステンのケイ化物は四フッ化炭素・酸素混合ガス中で
プラズマエツチングが可能である。このエツチングは一
部は鼾ンネル反応器内で、一部は平行板反応器内で陽極
結合の下に実施される。原理的にはこれらの層は湿式エ
ツチングが可能であるが、この場合湿式エツチングに通
例の寸法損失が起る。
According to this, silicides of titanium, tantalum, molybdenum, and tungsten can be plasma etched in a mixed gas of carbon tetrafluoride and oxygen. This etching is carried out partly in a tunnel reactor and partly in a parallel plate reactor under anodic bonding. In principle, these layers can be wet-etched, but the dimensional losses customary for wet etching occur in this case.

ヨーロッパ特許出願第0015403号明細書中にはポ
リシリコンに対する種々のプラズマエツチング法が記載
されているが、そこでは六フッ化イオン(SF6)、塩
素(012)および不活性ガスの混合物が使用される。
European Patent Application No. 0015403 describes various plasma etching methods for polysilicon, in which a mixture of hexafluoride ions (SF6), chlorine (012) and an inert gas is used. .

これらの方法ではケイ素だけが選択エッチされ、  5
io2と窒化ケイ素が共存する場合極めて良好な選択性
が達成される。更に腐蝕基板を高周波印加電極上に乗せ
、反応性のイオンエツチングに基いて指向性のエツチン
グを実施し1作られた凹みが垂直側壁を持ち、エツチン
グマスクがこの凹みの縁端を越えてはみ出さないように
することができる。
In these methods, only silicon is selectively etched, and 5
Very good selectivity is achieved when io2 and silicon nitride coexist. Furthermore, the corroded substrate is placed on a high-frequency application electrode, and directional etching is performed based on reactive ion etching.1 The created recess has vertical sidewalls, and the etching mask protrudes beyond the edge of this recess. You can avoid it.

冒頭に挙げた方法は既に提案されているものであるが、
そこでは六フッ化イオウがエツチングガスとして使用さ
れ、エツチング過程は腐蝕速度が□ 異る二つの段階に分けて実施される。この場合も厳格な
異方性腐蝕が望まれる。
The method mentioned at the beginning has already been proposed, but
There, sulfur hexafluoride is used as the etching gas, and the etching process is carried out in two stages with different corrosion rates. In this case as well, strict anisotropic corrosion is desired.

この発明による方法は金属ケイ化物、ボリンリコンニ重
層の腐蝕において従来の技術を凌駕するものであり、更
に二重ボリンリコンゲート過程においての傾斜エツチン
グあるいは段落の問題を隣り合った多結晶ケイ化物導体
路間の短絡をびき起すことなく解決するものである。こ
れらの問題点は第1図に矢印II、12および13をも
って示されている。
The method of the present invention surpasses prior art techniques in corroding metal silicide, borin recon two layers, and also eliminates the problem of slope etching or paragraphing between adjacent polycrystalline silicide conductor tracks in the double borin recon gate process. This solves the problem without causing a short circuit. These problems are indicated by arrows II, 12 and 13 in FIG.

この発明による方法は反応ガスとしてフッ素と塩素を含
む混合ガスが使用されることを特徴としている。例えば
六フッ化イオウのようなフッ素だけを含むエツチングガ
スを使用すると腐蝕部にオーバーハングが形成される。
The method according to the invention is characterized in that a mixed gas containing fluorine and chlorine is used as the reaction gas. For example, when an etching gas containing only fluorine, such as sulfur hexafluoride, is used, an overhang is formed in the corroded area.

又塩素をエツチングガスとするときは特にケイ化タンタ
ル層の場合腐蝕速度が極めて低くなる。六フッ比イオウ
(SF6)と塩素(SF2)から成る混合ガスを使用す
ることもこの発明の枠内にある。
Furthermore, when chlorine is used as the etching gas, the corrosion rate becomes extremely low, especially in the case of tantalum silicide layers. It is also within the scope of the invention to use a gas mixture consisting of sulfur hexafluoride (SF6) and chlorine (SF2).

塩素原子で置換されたフッ化炭化水素例えばモノクロル
トリフルオルメタン(cazy3)又はジクロルジフル
オルメタン(OCl2F 2 ) t−使用することも
可能である。
It is also possible to use fluorinated hydrocarbons substituted with chlorine atoms, such as monochlorotrifluoromethane (cazy3) or dichlorodifluoromethane (OCl2F2).

この発明の特に有利な実施例においては、厚さ約200
 n mのケイ化タンタル層(タンタル対ケイ素比1:
2)と厚さ300nmのn+ドープポリシリコン層から
成る二重層が使用される。
In a particularly advantageous embodiment of the invention, the thickness is approximately 200 mm.
n m tantalum silicide layer (tantalum to silicon ratio 1:
A double layer consisting of 2) and a 300 nm thick n+ doped polysilicon layer is used.

この発明のその他の実施態様は特許請求の範囲第2項以
下に示されている。
Other embodiments of the invention are shown in claims 2 and below.

この発明の詳細とその長所を実施例と第2図乃至第8図
について説明する。
The details of the invention and its advantages will be explained with reference to embodiments and FIGS. 2 to 8.

第2図にこの発明の方法によって作られた構造の断面を
示す。この構造は厚さ20nmの5102噛2で覆われ
たシリコン基板1の表面に設けられたD 型トープ(リ
ン又はヒ素)ポリシリコン層3とその上に厚さ200n
mに析出したケイ化タンタル層1から成る。5はエツチ
ングマスクとして使用された感光仙脂層である。タンタ
ル対ケイ素比は約1=2であシ、タンタルの割合は30
%から50%までの変動が許される。第2図には厳格な
異方性エツチングを目指したときの構造が示されている
。これは例えば二段階エツチングを採Jjl I〜、最
初にケイ化タンタル層4を塩素外の少ないエツチングガ
スでエッチし、恋にポリ/リコン層S3を純塩素中で処
理することによって達成される。この方法によりケイ化
物ポリシリジン二重層が完全に回り込み腐蝕無しに垂直
な縁端な持ってエッチされる。第一段1哲から第二段階
への切換点は例えばプラズマの適当な放出スペクトル線
の強度を記録することによって決定できる。同時に第二
段階において30:1以上とbう高い5it)2に対す
るポリシリコン選択性の達成が可能となる。
FIG. 2 shows a cross section of a structure made by the method of the invention. This structure consists of a D-type tope (phosphorus or arsenic) polysilicon layer 3 provided on the surface of a silicon substrate 1 covered with a 20 nm thick 5102 layer 2, and a 200 nm thick polysilicon layer 3 on top of the silicon substrate 1.
It consists of a tantalum silicide layer 1 deposited on m. 5 is a photosensitive sebum layer used as an etching mask. The tantalum to silicon ratio is approximately 1 = 2, and the tantalum ratio is 30
Variations from % to 50% are allowed. FIG. 2 shows a structure aimed at strict anisotropic etching. This can be achieved, for example, by employing a two-step etching process, first etching the tantalum silicide layer 4 with a chlorine-free etching gas and then treating the poly/licon layer S3 in pure chlorine. With this method, the silicide polysilidine bilayer is etched with vertical edges completely without corrosion. The switching point from the first stage to the second stage can be determined, for example, by recording the intensity of the appropriate emission spectral line of the plasma. At the same time, in the second step it is possible to achieve a high polysilicon selectivity for 5it)2 of 30:1 or higher.

二重層3,4の縁端面断面形状がエツチング混合ガスの
組成によって変形する情況は第3図に示されている。横
軸にはsy6:ct2の混合比をとり、縦軸Vては二重
層の腐蝕時間tW (単位分)をとる。図に破線でホモ
た曲線は腐蝕時間とガス組成の関係を表わす。構造aは
塩素分無しで長時間腐蝕したもの、構造すは極めて短い
腐蝕時間によるもの、構造Cは混合比SF6  : c
12=2:1において最も短い腐蝕時間によるものであ
る。構この断面形状はまだ使用可能である。構造θは混
合比SF5:C42=5 : 15をもって作られたも
ので°、ケイ化物に強い回り込み腐蝕が起っている。
The situation in which the cross-sectional shape of the edge surfaces of the double layers 3, 4 is deformed depending on the composition of the etching gas mixture is shown in FIG. The horizontal axis represents the mixing ratio of sy6:ct2, and the vertical axis V represents the corrosion time tW (in minutes) of the double layer. The dashed line in the figure represents the relationship between corrosion time and gas composition. Structure A is the result of long-term corrosion without chlorine content, Structure A is the result of extremely short corrosion time, and Structure C is the product with a mixing ratio of SF6:c.
This is due to the shortest corrosion time at 12=2:1. The structure's cross-sectional shape is still usable. The structure θ was made with a mixture ratio of SF5:C42=5:15°, and strong wrap-around corrosion occurred in the silicide.

混合比がSF6:C72=5 : 15のときこれより
も堰に良い異方性は低いガス圧(約10 m Torr
=]、5Pa)において達成される。
When the mixture ratio is SF6:C72=5:15, the anisotropy that is better for the weir than this is obtained by lower gas pressure (approximately 10 m Torr).
=], 5 Pa).

第3図に示すものではエツチング中の反応容器内のガス
圧は6乃至9Pa(=40乃至60mTorr )であ
り、高周波電力密度は約012W//crn2であった
In the case shown in FIG. 3, the gas pressure in the reaction vessel during etching was 6 to 9 Pa (=40 to 60 mTorr), and the high frequency power density was about 0.12 W//crn2.

第4図と第5図に腐蝕速度(n m7m1 n )とガ
ス圧(Pa)および高周波電力密度(Wa t t//
crn2)との関係を示す。矢印は記載された構造が作
られたときの条件を指り示している。
Figures 4 and 5 show the corrosion rate (n m7m1 n), gas pressure (Pa), and high frequency power density (Wat t//
crn2). The arrows point to the conditions under which the described structure was created.

第4図の場合高周波電力は01’W/−に調整され、混
合ガスの混合比はSF6:072:Hθ=12、.5:
8.5:20であった。X破線はケイ化タンタル、0破
線はポリシリコン、口破線は5io2に対するものであ
り、8破線は5102に対するポリシリコンの選択性を
示している。
In the case of FIG. 4, the high frequency power is adjusted to 01'W/-, and the mixture ratio of the mixed gas is SF6:072:Hθ=12, . 5:
It was 8.5:20. The X-dashed line shows the selectivity of tantalum silicide, the 0-dashed line shows the selectivity of polysilicon, the open-dashed line shows the selectivity of polysilicon with respect to 5io2, and the 8-dashed line shows the selectivity of polysilicon with respect to 5102.

高周波電力との関係を示した第5図においても曲線は第
4図と同じ意味を持つ。この場合反応器のガス圧は40
 m Torrであった。
In FIG. 5 showing the relationship with high frequency power, the curves have the same meaning as in FIG. 4. In this case, the gas pressure in the reactor is 40
mTorr.

第6図と第7図に示した腐蝕断面形状は混合ガス組成が
一定のとき反応器の形状即ちその全容積に対する実効プ
ラズマ容積の比に強く関係することが確められている。
It has been established that the corrosion profile shown in FIGS. 6 and 7 is strongly related to the shape of the reactor, ie, the ratio of effective plasma volume to its total volume, when the gas mixture composition is constant.

この容積比はプラズマ中の各種のラジカルの濃度分布に
影響を及ぼす。第6図に示した構造の場合反応器容積に
対するプラズマ能動容積の比は1:20以下であり、第
7図の場合は約1:2であって反応器容積の半分が能動
゛容積となっている。重要な差異は第6図ではケイ、化
物(上層)がtソてのSF6:ct2比において感光樹
脂マスクに関して異方性腐蝕を受けるのに対して、第7
図の場合ケイ化物の腐蝕情況はガス混合比によって第3
図に示したように異方性から強い回り込み腐蝕まで変化
することである。
This volume ratio affects the concentration distribution of various radicals in the plasma. In the structure shown in Figure 6, the ratio of the plasma active volume to the reactor volume is less than 1:20, and in the case of Figure 7, it is approximately 1:2, with half of the reactor volume being the active volume. ing. The important difference is that in Figure 6, the silicon compound (upper layer) undergoes anisotropic corrosion with respect to the photoresist mask at an SF6:ct2 ratio of t, whereas in Figure 7
In the case of the figure, the corrosion situation of silicides varies depending on the gas mixture ratio.
As shown in the figure, the corrosion changes from anisotropy to strong wraparound corrosion.

ポリシリコン・ケイ化物層3,4が/リコン基板に対す
る局部的の接触を心安とする場合には基板のある程度の
腐蝕は避けられない(第1図矢印+3参照)。これによ
って製造工程の終りにポリノリコンケイ化物層と基板の
間の抵抗が高くなる。
If the polysilicon silicide layers 3, 4 are to be in secure local contact with the /recon substrate, some corrosion of the substrate is inevitable (see arrow +3 in FIG. 1). This results in a high resistance between the polynosilicide layer and the substrate at the end of the manufacturing process.

lO:1まで高め、それによって基板の礪蝕を極めて少
量にとどめることができる。この事情を第8図に示す。
1O:1, thereby keeping the erosion of the substrate to an extremely small amount. This situation is shown in Figure 8.

図はn+ボリンリコン対単結晶シリコンの腐蝕速度比あ
るいはn+ポリンリコン対5102の選択性をSF6:
 ct2a合比に関係して示す。雇蝕速′度はSccm
 (標準状蝮tyn3毎分)で表わす。標準状態とは大
気圧、特定温度を意味する。
The figure shows the corrosion rate ratio of n+ borin recon vs. single crystal silicon or the selectivity of n+ borin recon vs. 5102 SF6:
It is shown in relation to the ct2a synthesis ratio. The erosion speed is Sccm
(expressed in standard tyn3 per minute). Standard conditions mean atmospheric pressure and specific temperature.

矢印1’+の曲線は選択性を表わし、矢印15の曲線は
腐蝕速度を表わす。記号口、Oは測定点を示している。
The curve with arrow 1'+ represents the selectivity and the curve with arrow 15 represents the corrosion rate. The symbol O indicates the measurement point.

ガス混合比SF6:O42の有利な値は5:15から2
:18の範囲である。
Advantageous values for the gas mixture ratio SF6:O42 are from 5:15 to 2
:18 range.

二重層3,4の構造形成をケイ化物の多結晶化と低抵抗
化のだめのテンパー熱処理の前に実施することもこの発
明の枠内にある。テンパー熱処理前はケイ化物・ポリシ
リコン境界面はテンパー熱処理後よりも遥に平滑である
。このことは二段階エツチングに際して切換点が明確に
決定されるという利点を持つ。
It is also within the scope of the invention to carry out the structural formation of the double layers 3, 4 before the tempering heat treatment for polycrystallization of the silicide and for lowering the resistance. Before tempering, the silicide-polysilicon interface is much smoother than after tempering. This has the advantage that the switching point is clearly determined during two-step etching.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、集積回路の製作に轟って注意すべき個所を示
す図面、第2図はこの発明の方法によって作られた構造
の断面図、第3図乃至第5図は最適エツチング条件をそ
れによって作られる構造と共(′こ示すダイヤグラムで
あり、第6図と第7図は反応容器容積対能動プラズマ答
積比の種々の値(でおいて作られる構造を示し、第8図
は単結晶シリコンに対するn+ドープポリシリコンの腐
蝕速1、il比あるいは5i02にlすするポリシリコ
ンの選択性を混合ガス組成に関係して示す。各図におい
て1 :ンリコン基板、2 : 5102 @、3:n
+ドープポリ/リコン層、4:ケイ化物層、5:感光樹
脂エツチングマスクである。 FIG 4 a      b        c l     5     [15Pa IG 5
FIG. 1 is a drawing showing the points that need to be taken into consideration when manufacturing an integrated circuit, FIG. 2 is a cross-sectional view of a structure made by the method of the present invention, and FIGS. 3 to 5 show the optimum etching conditions. Figures 6 and 7 show the structures produced at various values of the reaction vessel volume to active plasma response ratio, and Figure 8 shows the structures produced therewith. Corrosion rate of n+ doped polysilicon relative to single crystal silicon The selectivity of polysilicon to 1, il ratio or 5i02 is shown in relation to the mixed gas composition. In each figure 1: silicon substrate, 2: 5102 @, 3 :n
+doped poly/recon layer, 4: silicide layer, 5: photosensitive resin etching mask. FIG 4 a b c l 5 [15Pa IG 5

Claims (1)

【特許請求の範囲】 1)集積半導体回路を含む周板を平板形反応器(C入れ
、感九惨脂マスクを使用して反応ガス(/ζよって反応
性のイオ/エッチ/グを行なう際反応ガスとしてフッ素
と塩素を含む混合ガスを使用することを!l!′徴とす
る集積回路を含む基板の表面に金属ケイ化物・ポリ7リ
コンニ屯層の構造を作る方法。 2)反応ガスとして六フッ化イオウ(SF6)と塩素(
C62)から成る混合ガスが使用されることを特徴とす
る特許請求の範囲第1項記載の方法。 :))塩素1g> ’i’−で置Mさねたフッ化炭化水
素例えはモノクロルトリノルオルメタン又はジクロルジ
フルオルメタンが使用されることを特徴とする特許請求
の範囲第1項記載の方法。 4)ケイ化タンタル(TaSi2 )とポリシリコンか
ら成る二重層が使用されることを特徴とする特許請求の
範囲第1項乃至第3項のいずれかに記載の方法。 nmの1 ドープポリシリコン層から成ることを特徴と
する特許請求の範囲第4項記載の方法。 6)六フッ化イオウと塩素の混合ガスを使用する場合回
り込み腐蝕を起させるためsF6対ct2の混合比を2
;1とし、ガス圧を6〜9Paに1反応装置の高周波電
力を0.1乃至(1,14W / cm2 に調節する
ことを特徴とする特許請求の範囲第4JJ!又は第5項
記載の方法。 7)六フッ化イオウと塩素の混合ガスを使用する場合異
方性エツチングを行なうためエツチング過程を二段階に
分け、i&初はケイ化タンタル層を混合比が:3:1よ
り大きい六フッrヒイオウ・塩素混合ガスでエッチし、
次にポリの方法。 8)ポリ/リコン層に対して回り込み腐蝕を行なうため
六フッrヒイオウ対塩素の混合比を1:1としたとき反
応器内の反応ガス容積と反応器容積の比を1=20以下
に調整すること1))ケイ化タンタル層K 71 して
回り込み腐蝕を行なうため六フッfヒイオン対塩素の混
合比を1:1としたとき反応器内の有効反応容積と□ 反応器容積の比を[1=2に調整することを特11 徴とするI特許1清求の範囲第1項乃至第7項のいずれ
かにd[シ載の方法。 10)金属ケイ化物・ボリンリコ/二重層を結晶形に移
すために必要なテンパー熱処理の前に反応性イオンエツ
チングを実施することを特徴とする特許請求の範囲第1
項乃至第9項のいずれかに記載の方法。 11)ヘリウムのような希ガスを輸送ガスとして使用す
ることを特徴とする特許請求の範囲第1項乃至第10項
のいずれかに記載の方法。
[Claims] 1) A peripheral plate containing an integrated semiconductor circuit is placed in a flat plate reactor (C), and a reactive gas (/ζ) is etched using a reactive gas mask. A method for forming a metal silicide/poly7 silicon layer structure on the surface of a substrate containing an integrated circuit using a mixed gas containing fluorine and chlorine as a reactive gas. 2) As a reactive gas Sulfur hexafluoride (SF6) and chlorine (
2. Process according to claim 1, characterized in that a gas mixture consisting of C62) is used. :)) 1 g of chlorine the method of. 4) A method according to any one of claims 1 to 3, characterized in that a double layer of tantalum silicide (TaSi2) and polysilicon is used. 5. A method as claimed in claim 4, characterized in that it comprises a layer of doped polysilicon of 1 nm. 6) When using a mixed gas of sulfur hexafluoride and chlorine, the mixing ratio of sF6 to ct2 should be set to 2 to cause wraparound corrosion.
;1, the gas pressure is adjusted to 6 to 9 Pa, and the high frequency power of one reactor is adjusted to 0.1 to (1.14 W/cm2). 7) When using a mixed gas of sulfur hexafluoride and chlorine, the etching process is divided into two stages to perform anisotropic etching. Etch with a mixture of hydrogen and chlorine gas,
Next is the poly method. 8) In order to cause wraparound corrosion to the poly/recon layer, when the mixing ratio of hexafluoride to chlorine is set to 1:1, adjust the ratio of the reaction gas volume in the reactor to the reactor volume to 1 = 20 or less. 1)) In order to cause wraparound corrosion in the tantalum silicide layer K 71 , when the mixing ratio of hexafluoride ions to chlorine is 1:1, the ratio of the effective reaction volume in the reactor to the reactor volume is [ The method described in any one of the scope of claims 1 to 7 of I Patent 1, which is characterized by adjusting 1=2. 10) Reactive ion etching is carried out before the tempering heat treatment necessary to transfer the metal silicide/borinlico/bilayer to crystalline form.
The method according to any one of Items 9 to 9. 11) A method according to any one of claims 1 to 10, characterized in that a rare gas such as helium is used as the transport gas.
JP58078103A 1982-05-05 1983-05-02 Method of fabricating metal silicide-polysilicon bilayer structures on substrates containing integrated circuits Pending JPS58204538A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE32168233 1982-05-05
DE19823216823 DE3216823A1 (en) 1982-05-05 1982-05-05 METHOD FOR PRODUCING STRUCTURES OF DOUBLE LAYERS CONSISTING OF METAL SILICIDE AND POLYSILIZIUM ON SUBSTRATES CONTAINING INTEGRATED SEMICONDUCTOR CIRCUITS BY REACTIVE ION NETWORK

Publications (1)

Publication Number Publication Date
JPS58204538A true JPS58204538A (en) 1983-11-29

Family

ID=6162783

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Country Status (4)

Country Link
US (1) US4473436A (en)
EP (1) EP0094528A3 (en)
JP (1) JPS58204538A (en)
DE (1) DE3216823A1 (en)

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Also Published As

Publication number Publication date
EP0094528A3 (en) 1987-05-06
EP0094528A2 (en) 1983-11-23
US4473436A (en) 1984-09-25
DE3216823A1 (en) 1983-11-10

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