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JPS57210632A - Forming method for wiring pattern - Google Patents

Forming method for wiring pattern

Info

Publication number
JPS57210632A
JPS57210632A JP9483181A JP9483181A JPS57210632A JP S57210632 A JPS57210632 A JP S57210632A JP 9483181 A JP9483181 A JP 9483181A JP 9483181 A JP9483181 A JP 9483181A JP S57210632 A JPS57210632 A JP S57210632A
Authority
JP
Japan
Prior art keywords
layer
oxidized
photosensitive resin
plasma
hno3
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9483181A
Other languages
Japanese (ja)
Inventor
Yorihiro Uchiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9483181A priority Critical patent/JPS57210632A/en
Publication of JPS57210632A publication Critical patent/JPS57210632A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To facilitate oxygen plasma ashing by treating the surface of photosensitive resin degenerated through dry etching by the mixed liquid of nitric acid and H2O2. CONSTITUTION:When a material obtained by forming an insulating layer 12 and a photosensitive resin layer 14 onto a semiconductor substrate 11 is etched by a gas such as CF4, the surface of the layer 14 is changed into a degenerated layer 15. The whole is immersed in a liquid obtained by adding H2O2 to HNO3 at a 5-6% molar ratio or a strong-acidic liquid 16 acquired by adding water to HNO3 at the volume ratio of 0-2 for three or five min and oxidized in wet form. When the whole is incinerated by O2 plasma, the oxidized degenerate layer is incinerated and removed together with the photosensitive resin 14 because resistance against O2 plasma is weakened in the oxidized degenerate layer, and foreign matters do not adhere on an Al wiring layer exposed.
JP9483181A 1981-06-19 1981-06-19 Forming method for wiring pattern Pending JPS57210632A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9483181A JPS57210632A (en) 1981-06-19 1981-06-19 Forming method for wiring pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9483181A JPS57210632A (en) 1981-06-19 1981-06-19 Forming method for wiring pattern

Publications (1)

Publication Number Publication Date
JPS57210632A true JPS57210632A (en) 1982-12-24

Family

ID=14120986

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9483181A Pending JPS57210632A (en) 1981-06-19 1981-06-19 Forming method for wiring pattern

Country Status (1)

Country Link
JP (1) JPS57210632A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02262335A (en) * 1989-03-31 1990-10-25 Toshiba Corp Eliminating method of organic compound film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02262335A (en) * 1989-03-31 1990-10-25 Toshiba Corp Eliminating method of organic compound film

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