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JPS57167622A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57167622A
JPS57167622A JP56053299A JP5329981A JPS57167622A JP S57167622 A JPS57167622 A JP S57167622A JP 56053299 A JP56053299 A JP 56053299A JP 5329981 A JP5329981 A JP 5329981A JP S57167622 A JPS57167622 A JP S57167622A
Authority
JP
Japan
Prior art keywords
layer
thermal expansion
silicon dioxide
silicate glass
expansion coefficient
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56053299A
Other languages
Japanese (ja)
Inventor
Junji Sakurai
Tetsushi Wakabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56053299A priority Critical patent/JPS57167622A/en
Publication of JPS57167622A publication Critical patent/JPS57167622A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0272—Deposition of sub-layers, e.g. to promote the adhesion of the main coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To avoid the generation of cracking in an insulation layer when a semiconductor layer is formed by a method wherein an intermediate layer, which relieves the stress caused by the difference between the thermal expansion coefficient of the substrate and that of the insulation layer, is formed on the surface of a substrate and the insulation layer is formed on this intermediate layer. CONSTITUTION:An alimina boron silicate glass layer 12 the thermal expansion coefficient of which is approximately 20X10<-7>/ deg.C is formed on a ceramic substrate 11 the thermal expansion coefficient of which is approximately 70X10<-7>/ deg.C as an intermediate layer. Then a silicon dioxide layer 13 is formed on the alumina boron silicate glass layer 12 as an insulation layer. With this constitution, when a semiconductor layer 14 is formed on the silicon dioxide layer 13 by vapor phase growth method, the stress caused by the difference of the thermal expansion coefficients of the silicon dioxide layer 13 and the ceramic substrate 11 is relieved by the alumina boron silicate glass layer 12 and the generation of cracking in the silicon dioxide layer 13 is avoided.
JP56053299A 1981-04-09 1981-04-09 Manufacture of semiconductor device Pending JPS57167622A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56053299A JPS57167622A (en) 1981-04-09 1981-04-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56053299A JPS57167622A (en) 1981-04-09 1981-04-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57167622A true JPS57167622A (en) 1982-10-15

Family

ID=12938837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56053299A Pending JPS57167622A (en) 1981-04-09 1981-04-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57167622A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5317068A (en) * 1976-07-30 1978-02-16 Fujitsu Ltd Semiconductor device and its production

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5317068A (en) * 1976-07-30 1978-02-16 Fujitsu Ltd Semiconductor device and its production

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