JPS57162349A - Forming method for multilayer wiring of semiconductor device - Google Patents
Forming method for multilayer wiring of semiconductor deviceInfo
- Publication number
- JPS57162349A JPS57162349A JP4561781A JP4561781A JPS57162349A JP S57162349 A JPS57162349 A JP S57162349A JP 4561781 A JP4561781 A JP 4561781A JP 4561781 A JP4561781 A JP 4561781A JP S57162349 A JPS57162349 A JP S57162349A
- Authority
- JP
- Japan
- Prior art keywords
- fine metallic
- film
- metallic wire
- wire
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To improve the reliability by forming the interlayer insuating film to the height of a fine metallic wire in the state that the temperature of an insulating film is increased higher than the fine metallic wire with infrared ray emission on the insulating film and the first layer via the fine metallic wire on a substrate and further growing the insulating film. CONSTITUTION:A fine metallic wire 23 of the first layer is selectivley formed on the insulating film 22 of a substrate 21. This is filled in a pen-jar of a CVD device and infrared ray is emitted. Then, the temperature of the film 22 made of substance absorbing the heat beam is raised, and the temperature of the fine metallic wire is lowered. Accordingly, the SiO2 film to be formed is thick on the insulating film and thin on the fine metallic wire. Then, the infrared ray emission is stopped, the second fine metallic wire 27 is formed on the film 26 of the interlayer insualting film as a multilayer wire. Thus, the stepped part of the multilayer wire can be reduced, thereby preventing the breakage of the wire and enhancing the reliability.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4561781A JPS57162349A (en) | 1981-03-30 | 1981-03-30 | Forming method for multilayer wiring of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4561781A JPS57162349A (en) | 1981-03-30 | 1981-03-30 | Forming method for multilayer wiring of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57162349A true JPS57162349A (en) | 1982-10-06 |
Family
ID=12724333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4561781A Pending JPS57162349A (en) | 1981-03-30 | 1981-03-30 | Forming method for multilayer wiring of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57162349A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5089442A (en) * | 1990-09-20 | 1992-02-18 | At&T Bell Laboratories | Silicon dioxide deposition method using a magnetic field and both sputter deposition and plasma-enhanced cvd |
| US5322806A (en) * | 1988-08-24 | 1994-06-21 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a semiconductor device using electron cyclotron resonance plasma CVD and substrate biasing |
-
1981
- 1981-03-30 JP JP4561781A patent/JPS57162349A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5322806A (en) * | 1988-08-24 | 1994-06-21 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a semiconductor device using electron cyclotron resonance plasma CVD and substrate biasing |
| US5089442A (en) * | 1990-09-20 | 1992-02-18 | At&T Bell Laboratories | Silicon dioxide deposition method using a magnetic field and both sputter deposition and plasma-enhanced cvd |
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