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JPS57153323A - Information process controller - Google Patents

Information process controller

Info

Publication number
JPS57153323A
JPS57153323A JP3899181A JP3899181A JPS57153323A JP S57153323 A JPS57153323 A JP S57153323A JP 3899181 A JP3899181 A JP 3899181A JP 3899181 A JP3899181 A JP 3899181A JP S57153323 A JPS57153323 A JP S57153323A
Authority
JP
Japan
Prior art keywords
request
priority determining
gate
time
determining circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3899181A
Other languages
Japanese (ja)
Inventor
Shukichi Moriyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3899181A priority Critical patent/JPS57153323A/en
Publication of JPS57153323A publication Critical patent/JPS57153323A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To achieve urgent transmission from a central processor to other device, by determining prioity with a waiting time, contents of request and types of data processors. CONSTITUTION:Counters CNT0-CNT3 count a time waited for a request corresponding to a request source and outputs an overflow C when the time reaches a prescribed time. The order of request execution of a data input and output device DCH0/1 is stored with a flip-flop PT0. The temporary suppressing means of execution of request consists of a priority determining circuit PTY0 and an AND gate 2. The 1at priority determining means consists of a priority determining circuit PTY1 and an AND gate 4, and the 2nd priority determining means consists of a priority determining circuit PTY2, an NAND gate 5, an AND gate 6, a flip-flop PT0 and a PT1.
JP3899181A 1981-03-17 1981-03-17 Information process controller Pending JPS57153323A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3899181A JPS57153323A (en) 1981-03-17 1981-03-17 Information process controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3899181A JPS57153323A (en) 1981-03-17 1981-03-17 Information process controller

Publications (1)

Publication Number Publication Date
JPS57153323A true JPS57153323A (en) 1982-09-21

Family

ID=12540599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3899181A Pending JPS57153323A (en) 1981-03-17 1981-03-17 Information process controller

Country Status (1)

Country Link
JP (1) JPS57153323A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62214467A (en) * 1986-03-17 1987-09-21 Fujitsu Ltd Multiprocessor instruction control system
JPS63211438A (en) * 1987-02-27 1988-09-02 Nec Corp Interruption control circuit
JPH03102441A (en) * 1989-09-16 1991-04-26 Nec Corp Storage device
JPH0535503A (en) * 1991-07-25 1993-02-12 Nec Corp Interruption control circuit
JP2003131937A (en) * 2001-08-31 2003-05-09 Koninkl Philips Electronics Nv Dynamic access control for handling grouped resources
JP2014038544A (en) * 2012-08-20 2014-02-27 Fujitsu Ltd Arithmetic processing unit and method for controlling arithmetic processing unit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62214467A (en) * 1986-03-17 1987-09-21 Fujitsu Ltd Multiprocessor instruction control system
JPS63211438A (en) * 1987-02-27 1988-09-02 Nec Corp Interruption control circuit
JPH03102441A (en) * 1989-09-16 1991-04-26 Nec Corp Storage device
JPH0535503A (en) * 1991-07-25 1993-02-12 Nec Corp Interruption control circuit
JP2003131937A (en) * 2001-08-31 2003-05-09 Koninkl Philips Electronics Nv Dynamic access control for handling grouped resources
JP2014038544A (en) * 2012-08-20 2014-02-27 Fujitsu Ltd Arithmetic processing unit and method for controlling arithmetic processing unit

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