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JPS5798025A - Channel controller - Google Patents

Channel controller

Info

Publication number
JPS5798025A
JPS5798025A JP55173991A JP17399180A JPS5798025A JP S5798025 A JPS5798025 A JP S5798025A JP 55173991 A JP55173991 A JP 55173991A JP 17399180 A JP17399180 A JP 17399180A JP S5798025 A JPS5798025 A JP S5798025A
Authority
JP
Japan
Prior art keywords
address
channel
rear bus
cpu1
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55173991A
Other languages
Japanese (ja)
Inventor
Kazumasa Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55173991A priority Critical patent/JPS5798025A/en
Publication of JPS5798025A publication Critical patent/JPS5798025A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Retry When Errors Occur (AREA)

Abstract

PURPOSE:To reduce the load of software and promote speed-up of processing by retrieving the address storage section of a rear bus, finding out the corresponding rear bus address and executing again input/output access with the address. CONSTITUTION:When there is a request for starting input/output (I/O) operation from a CPU1-2, a controller for interruption 7 decodes the bus address of an assigned I/O device, transfers this I/O request through a section controlling channel interface 11 to the channel of a channel unit and starts I/O opertion. In this case, if the channel device is put into operation and busy or an unusable state due to trouble, then, the CPU1 retrieves the address storage section in the rear bus 14, finds out the corresponding rear bus address, and executes again the I/O access with the address.
JP55173991A 1980-12-10 1980-12-10 Channel controller Pending JPS5798025A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55173991A JPS5798025A (en) 1980-12-10 1980-12-10 Channel controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55173991A JPS5798025A (en) 1980-12-10 1980-12-10 Channel controller

Publications (1)

Publication Number Publication Date
JPS5798025A true JPS5798025A (en) 1982-06-18

Family

ID=15970737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55173991A Pending JPS5798025A (en) 1980-12-10 1980-12-10 Channel controller

Country Status (1)

Country Link
JP (1) JPS5798025A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015729A (en) * 1983-07-06 1985-01-26 Fujitsu Ltd Input and output control system
JPS60142454A (en) * 1983-12-28 1985-07-27 Fujitsu Ltd Input/output control method
JPS6184741A (en) * 1984-09-29 1986-04-30 Hitachi Ltd Interrupt control method
JPH05143484A (en) * 1992-05-13 1993-06-11 Hitachi Ltd Interrupt control method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015729A (en) * 1983-07-06 1985-01-26 Fujitsu Ltd Input and output control system
JPS60142454A (en) * 1983-12-28 1985-07-27 Fujitsu Ltd Input/output control method
JPS6184741A (en) * 1984-09-29 1986-04-30 Hitachi Ltd Interrupt control method
JPH05143484A (en) * 1992-05-13 1993-06-11 Hitachi Ltd Interrupt control method

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