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JPS5696313A - Bus control device of multiprocessor system - Google Patents

Bus control device of multiprocessor system

Info

Publication number
JPS5696313A
JPS5696313A JP16302479A JP16302479A JPS5696313A JP S5696313 A JPS5696313 A JP S5696313A JP 16302479 A JP16302479 A JP 16302479A JP 16302479 A JP16302479 A JP 16302479A JP S5696313 A JPS5696313 A JP S5696313A
Authority
JP
Japan
Prior art keywords
bus
req
request
generated
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16302479A
Other languages
Japanese (ja)
Inventor
Eiichi Kagawa
Nobuaki Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16302479A priority Critical patent/JPS5696313A/en
Publication of JPS5696313A publication Critical patent/JPS5696313A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To make it possible that respective processors occupy a bus equally, by controlling variably the priority of bus requests in the bus control device, in the system where plural processors share devices with the common bus.
CONSTITUTION: Bus request signals REQ1WREQn from plural processors (PC) are input to priority encoder 7 through gate circuits 121W12n for the request mask of the bus control device. Binary output signals B1WBm of encoder 7 are input to zero detecting circuit 10 and decoder 8. When contents of signals B1WBm are zero, circuit 10 sets request mask FFs 111W11n and opens circuits 121W12n. When signals REQ1WREQn are simultaneously generated, the priority is selected by encoder 7, and signal A1 is output in decoder 8, and the FF for bus permission is set, and not only bus permission signal ACK1 is generated but also FF111 is reset and circuit 121 is closed. Thus, even when REQ1 is generated again after the completion of REQ1, the precedence of the preceding request is taken if another request signal is generated.
COPYRIGHT: (C)1981,JPO&Japio
JP16302479A 1979-12-12 1979-12-12 Bus control device of multiprocessor system Pending JPS5696313A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16302479A JPS5696313A (en) 1979-12-12 1979-12-12 Bus control device of multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16302479A JPS5696313A (en) 1979-12-12 1979-12-12 Bus control device of multiprocessor system

Publications (1)

Publication Number Publication Date
JPS5696313A true JPS5696313A (en) 1981-08-04

Family

ID=15765728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16302479A Pending JPS5696313A (en) 1979-12-12 1979-12-12 Bus control device of multiprocessor system

Country Status (1)

Country Link
JP (1) JPS5696313A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6180352A (en) * 1984-09-27 1986-04-23 Fujitsu Ltd Multiprocessor control system
JPS61166670A (en) * 1985-01-18 1986-07-28 Fujitsu Ltd Bus switching system for service processor
JPS6295653A (en) * 1985-10-22 1987-05-02 Nippon Telegr & Teleph Corp <Ntt> Competition control circuit
JPS62140160A (en) * 1985-12-16 1987-06-23 Nippon Telegr & Teleph Corp <Ntt> Self-synchronous competition control circuit
US5481726A (en) * 1992-08-28 1996-01-02 Mitsubishi Denki Kabushiki Kaisha Information processing system having a plurality of processors

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6180352A (en) * 1984-09-27 1986-04-23 Fujitsu Ltd Multiprocessor control system
JPS61166670A (en) * 1985-01-18 1986-07-28 Fujitsu Ltd Bus switching system for service processor
JPS6295653A (en) * 1985-10-22 1987-05-02 Nippon Telegr & Teleph Corp <Ntt> Competition control circuit
JPS62140160A (en) * 1985-12-16 1987-06-23 Nippon Telegr & Teleph Corp <Ntt> Self-synchronous competition control circuit
US5481726A (en) * 1992-08-28 1996-01-02 Mitsubishi Denki Kabushiki Kaisha Information processing system having a plurality of processors

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