JPS57166625A - Bus using right control system - Google Patents
Bus using right control systemInfo
- Publication number
- JPS57166625A JPS57166625A JP56049369A JP4936981A JPS57166625A JP S57166625 A JPS57166625 A JP S57166625A JP 56049369 A JP56049369 A JP 56049369A JP 4936981 A JP4936981 A JP 4936981A JP S57166625 A JPS57166625 A JP S57166625A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- processor
- inverted
- signal
- sets
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Small-Scale Networks (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE:Not only to omit a common part for controlling priority of a bus but also to elevate working efficiency of the bus, by constituting so that the next bus using right is given to a processor sending a bus use request signal, when the bus is being used. CONSTITUTION:An inverted REQ1 is set by a bus using request REQ1 of the first processor. In accordance with this request, both of delay line outputs RQL1, RQL2 of 2 processors become H, therefore, it is prevented that an REQ2 signal generated by the second processor is set to an FF 30. After that, each processor 1 sets output signals iINH1,2 of a delay line 21 to H after a constant interval of time. As a result, an AND gate 15 is opened, and a state which is capable of outputting a bus using signal inverted BSY is obtained. The first processor sets an FF 31 by an output of the gate 15, occupies a bus, also resets the FF 30, and sets in to a state which is capable of controlling the next bus using priority. The second processor is capable of obstructing to set the FF 30, but when the first processor outputs an inverted BSY signal, the using right is obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56049369A JPS609305B2 (en) | 1981-04-03 | 1981-04-03 | Bus right control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56049369A JPS609305B2 (en) | 1981-04-03 | 1981-04-03 | Bus right control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57166625A true JPS57166625A (en) | 1982-10-14 |
| JPS609305B2 JPS609305B2 (en) | 1985-03-09 |
Family
ID=12829102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56049369A Expired JPS609305B2 (en) | 1981-04-03 | 1981-04-03 | Bus right control method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS609305B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60150158A (en) * | 1983-09-22 | 1985-08-07 | デイジタル イクイプメント コ−ポレ−シヨン | Control mechanism for multiprocessor system |
| JPH06110825A (en) * | 1992-09-30 | 1994-04-22 | Nec Corp | Common bus control system |
-
1981
- 1981-04-03 JP JP56049369A patent/JPS609305B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60150158A (en) * | 1983-09-22 | 1985-08-07 | デイジタル イクイプメント コ−ポレ−シヨン | Control mechanism for multiprocessor system |
| JPH06110825A (en) * | 1992-09-30 | 1994-04-22 | Nec Corp | Common bus control system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS609305B2 (en) | 1985-03-09 |
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