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JPS57147249A - Manufacture of semiconductor integrated circuit - Google Patents

Manufacture of semiconductor integrated circuit

Info

Publication number
JPS57147249A
JPS57147249A JP3160281A JP3160281A JPS57147249A JP S57147249 A JPS57147249 A JP S57147249A JP 3160281 A JP3160281 A JP 3160281A JP 3160281 A JP3160281 A JP 3160281A JP S57147249 A JPS57147249 A JP S57147249A
Authority
JP
Japan
Prior art keywords
layer
polycrystalline silicon
implanted
boron
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3160281A
Other languages
Japanese (ja)
Inventor
Satoshi Shinozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3160281A priority Critical patent/JPS57147249A/en
Priority to DE19813129558 priority patent/DE3129558A1/en
Publication of JPS57147249A publication Critical patent/JPS57147249A/en
Priority to US06/507,557 priority patent/US4507849A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To form a V-shaped groove on a polycrystalline silicon with good flatness by selectively implanting boron ions in the V-shaped groove formed on a silicon epitaxial layer, and selectively removing the polycrystalline silicon devoid of any added substance. CONSTITUTION:After a buried layer 2, a silicon epitaxial layer 3, an oxidized film 5 and a polycrystalline silicon layer 6 are formed on a substrate 1, boron ions are implanted. The boron is implanted in the layer 6 on the inner surface of the groove 4, but is not implanted in the flat portion. When the layer 6 is then etched, only the layer 6 of the flat portion is etched. Subsequently, a polycrystalline silicon layer 7 is accumulated, the boron is diffused, and a polycrystalline silicon layer 7' is formed. Thereafter, the layer 7 is removed, and a flat element isolating region 9 is formed.
JP3160281A 1980-07-28 1981-03-05 Manufacture of semiconductor integrated circuit Pending JPS57147249A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP3160281A JPS57147249A (en) 1981-03-05 1981-03-05 Manufacture of semiconductor integrated circuit
DE19813129558 DE3129558A1 (en) 1980-07-28 1981-07-27 METHOD FOR PRODUCING AN INTEGRATED SEMICONDUCTOR CIRCUIT
US06/507,557 US4507849A (en) 1980-07-28 1983-06-24 Method of making isolation grooves by over-filling with polycrystalline silicon having a difference in impurity concentration inside the grooves followed by etching off the overfill based upon this difference

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3160281A JPS57147249A (en) 1981-03-05 1981-03-05 Manufacture of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS57147249A true JPS57147249A (en) 1982-09-11

Family

ID=12335742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3160281A Pending JPS57147249A (en) 1980-07-28 1981-03-05 Manufacture of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS57147249A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009034717A (en) * 2007-08-03 2009-02-19 Mitsubishi Materials Corp Casting equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009034717A (en) * 2007-08-03 2009-02-19 Mitsubishi Materials Corp Casting equipment

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