JPS57103328A - Semiconductor and manufacture thereof - Google Patents
Semiconductor and manufacture thereofInfo
- Publication number
- JPS57103328A JPS57103328A JP16412480A JP16412480A JPS57103328A JP S57103328 A JPS57103328 A JP S57103328A JP 16412480 A JP16412480 A JP 16412480A JP 16412480 A JP16412480 A JP 16412480A JP S57103328 A JPS57103328 A JP S57103328A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- layer
- sio2
- buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 3
- 239000004065 semiconductor Substances 0.000 title abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 8
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 150000002500 ions Chemical class 0.000 abstract 4
- 239000010410 layer Substances 0.000 abstract 4
- 239000000377 silicon dioxide Substances 0.000 abstract 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 239000000758 substrate Substances 0.000 abstract 3
- 239000002344 surface layer Substances 0.000 abstract 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000007547 defect Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
PURPOSE:To enhance the manufacturing yield of a semiconductor by implanting impurity ions to the groove surface layer when an isolating region is formed on a semiconductor substrate, heat treating it to activate the ion implanted region, using it as grounding region, thereby preventing the creeping of a buried region and production of crystalline defect. CONSTITUTION:An N<+> type buried region 2 is diffused in the prescribed region of a P<-> type Si substrate 1, an N type layer 3 is epitaxially grown on the overall surface including the region 2, and an SiO2 film 12, an Si3N4 film 13 and a photoresist layer 14 are laminated thereon. Then, V-shaped groove forming windows 15 are opened at the layer 14, are then etched to intrude the V-shaped grooves 4 surrounding the region 2 into the substrate 1, with the photoresist as a mask B<+> ions are implanted on the surface layer of the grooves 4, is heat treated, and activated for the ion implanting region, thereby forming a P<+> type region 18 and an SiO2 and an SiO2 5' disposed on the surface layer are formed. Thereafter, polycrystalline Si layer 6 is buried in the groove 4, is heated treated to convert the periphery into an SiO2 film 5, and the P type grounding region 11 contacted with the region 18 simultaneously upon formation of the P type base region 19 is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16412480A JPS57103328A (en) | 1980-11-21 | 1980-11-21 | Semiconductor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16412480A JPS57103328A (en) | 1980-11-21 | 1980-11-21 | Semiconductor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57103328A true JPS57103328A (en) | 1982-06-26 |
Family
ID=15787194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16412480A Pending JPS57103328A (en) | 1980-11-21 | 1980-11-21 | Semiconductor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57103328A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63245939A (en) * | 1987-03-31 | 1988-10-13 | Nec Corp | Semiconductor device |
-
1980
- 1980-11-21 JP JP16412480A patent/JPS57103328A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63245939A (en) * | 1987-03-31 | 1988-10-13 | Nec Corp | Semiconductor device |
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