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JPS57133646A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Semiconductor integrated circuit device and manufacture thereof

Info

Publication number
JPS57133646A
JPS57133646A JP56019463A JP1946381A JPS57133646A JP S57133646 A JPS57133646 A JP S57133646A JP 56019463 A JP56019463 A JP 56019463A JP 1946381 A JP1946381 A JP 1946381A JP S57133646 A JPS57133646 A JP S57133646A
Authority
JP
Japan
Prior art keywords
film
layer
groove
whole surface
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56019463A
Other languages
Japanese (ja)
Inventor
Toshihiko Fukuyama
Yoshinobu Monma
Ryoji Abe
Akira Tabata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56019463A priority Critical patent/JPS57133646A/en
Publication of JPS57133646A publication Critical patent/JPS57133646A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain the insulation isolation free from bird's beaks by a method wherein, when an IC device is insulation-isolated using a delivative, a U-shape isolation groove is provided surrounding an active region, the groove is filled up with a PSG film through the intermediaries of an SiO2 film and an Si3N4 film, and then the surface of the above is covered by an SiO2 film by performing oxidation of a polycrystalline Si. CONSTITUTION:An N<+> type buried layer 19 is formed by diffusion on a P type Si substrate 11, an N type layer 12 is epitaxially grown on the whole surface including the layer 19, and an SiO2 film 20 and an Si3N4 film 21 are laminated and coated on the whole surface. Then the active region 18, located on a layer 19, is covered with photoresist pattern 22, a dry etching is performed, a U-shape groove 13 entering into the substrate 11 is provided, and the region 18 is formed into an island shape. Subsequently, the pattern 22 is removed, an SiO2 film 14 which will be connected to the film 20 is coated on the exposed surface of the groove 13, a PSG film 15 is laminated on the whole surface along the film 14, the film 15 is fused by performing heat treatment, and the groove 13 is filled up with the film 15. Then, a polycrystalline Si layer 24 is grown on the whole surface, the layer 24 is converted to an SiO2 film 16 by performing heat treatment, and the region 18 is delivative-isolated using the films 15 and 16.
JP56019463A 1981-02-12 1981-02-12 Semiconductor integrated circuit device and manufacture thereof Pending JPS57133646A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56019463A JPS57133646A (en) 1981-02-12 1981-02-12 Semiconductor integrated circuit device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56019463A JPS57133646A (en) 1981-02-12 1981-02-12 Semiconductor integrated circuit device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS57133646A true JPS57133646A (en) 1982-08-18

Family

ID=12000013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56019463A Pending JPS57133646A (en) 1981-02-12 1981-02-12 Semiconductor integrated circuit device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS57133646A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827342A (en) * 1981-07-27 1983-02-18 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン Method of forming dielectric isolation region
JPS6020530A (en) * 1983-07-14 1985-02-01 Nec Corp Forming method of element isolation region
JPS61114549A (en) * 1984-11-09 1986-06-02 Nec Corp Manufacture of semiconductor integrated circuit device
JPH0685413B2 (en) * 1984-11-01 1994-10-26 エヌ・シー・アール・インターナショナル・インコーポレイテッド Method for forming insulating region on semiconductor substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827342A (en) * 1981-07-27 1983-02-18 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン Method of forming dielectric isolation region
JPS6020530A (en) * 1983-07-14 1985-02-01 Nec Corp Forming method of element isolation region
JPH0685413B2 (en) * 1984-11-01 1994-10-26 エヌ・シー・アール・インターナショナル・インコーポレイテッド Method for forming insulating region on semiconductor substrate
JPS61114549A (en) * 1984-11-09 1986-06-02 Nec Corp Manufacture of semiconductor integrated circuit device

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